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hd404849 series 4-bit single-chip microcomputer rev. 6.0 sept. 1998 description the hd404849 series of hmcs400-series microcomputers is designed to increase program productivity and also incorporate large-capacity memory. each microcomputer has an lcd controller/driver, a/d converter, input capture circuit, 32-khz oscillator for clock use, and four low-power dissipation modes. the hd404849 series includes the HD404848 with an 8-kword on-chip rom, the hd4048412 with a 12- kword on-chip rom, the hd404849 with a 16-kword on-chip rom, and the hd4074849 with a 16-kword on-chip prom. on-chip rom is available in a prom (ztat ? microcomputer) version and a mask rom version. a program can be written to the prom by a prom writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. prom programming specifications are the same as for the 27256. ztat ? : zero turn around time ztat is a trademark of hitachi ltd. features 35 i/o pins, including nine high-current pins (15 ma, max.), eight pins multiplexed with lcd segment pins, and four pins multiplexed with analog input pins four timer/counters eight-bit input capture circuit three timer outputs (including two pwm outputs) two event counter inputs (including one in which the detection edge is programmable) clock-synchronous 8-bit serial interface a/d converter (8 channels 8 bits) ? operation voltage 2.7 v to 6.0 v lcd driver (32 segments 4 commons) built-in oscillators ? main clock: can be driven by ceramic oscillator, crystal oscillator, or external clock. ? subclock: 32.768-khz crystal ten interrupt sources ? four by external sources, including two in which the detection edge is programmable
hd404849 series 2 ? six by internal sources subroutine stack up to 16 levels, including interrupts four low-power dissipation modes ? standby mode ? stop mode ? watch mode ? subactive mode one external input for transition from stop mode to active mode instruction cycle time: 0.89 m s (f osc = 4.5 mhz) operation voltage ? v cc = 2.7 v to 6.0 v (subactive mode: 2.2 v to 6.0 v) (HD404848, hd404849) ? v cc = 2.7 v to 5.5 v (hd4074849) two operating modes ? mcu mode (HD404848, hd4048412, hd404849) ? mcu/prom mode (hd4074849 only) ordering information type product name model name rom (words) ram (digits) package mask rom HD404848 HD404848h 8,192 512 80-pin plastic qfp (fp-80a) HD404848fs 80-pin plastic qfp (fp-80b) HD404848tf 80-pin plastic tqfp (tfp-80c) hd4048412 hd4048412h 12,288 1,184 80-pin plastic qfp (fp-80a) hd4048412fs 80-pin plastic qfp (fp-80b) hd4048412tf 80-pin plastic tqfp (tfp-80c) hd404849 hd404849h 16,384 1,184 80-pin plastic qfp (fp-80a) hd404849fs 80-pin plastic qfp (fp-80b) hd404849tf 80-pin plastic tqfp (tfp-80c) ztat ? hd4074849 hd4074849h 16,384 1,184 80-pin plastic qfp (fp-80a) hd4074849fs 80-pin plastic qfp (fp-80b) hd4074849tf 80-pin plastic tqfp (tfp-80c)
hd404849 series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r3 2 /an 6 r3 3 /an 7 av ss test osc 1 osc 2 reset x1 x2 gnd d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 10 / stopc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 d 11 / int 0 r0 0 / int 1 r0 1 /int 2 r0 2 /int 3 r0 3 r1 0 /tob r1 1 /toc r1 2 /tod r1 3 / evnb r2 0 /evnd r2 1 / sck r2 2 /si r2 3 /so r6 0 /seg13 r6 1 /seg14 r6 2 /seg15 r6 3 /seg16 r7 0 /seg17 r7 1 /seg18 r7 2 /seg19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 r3 1 /an 5 r3 0 /an 4 an 3 an 2 an 1 an 0 av cc v cc v 3 v 2 v 1 com4 com3 com2 com1 seg44 seg43 seg42 seg41 seg40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 r7 3 /seg20 fp-80a tfp-80c (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r3 0 /an 4 r3 1 /an 5 r3 2 /an 6 r3 3 /an 7 av ss test osc 1 osc 2 reset x1 x2 gnd d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 r0 1 /int 2 r0 2 /int 3 r0 3 r1 0 /tob r1 1 /toc r1 2 /tod r1 3 / evnb r2 0 /evnd r2 1 / sck r2 2 /si r2 3 /so r6 0 /seg13 r6 1 /seg14 r6 2 /seg15 r6 3 /seg16 r7 0 /seg17 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 an 3 an 2 an 1 an 0 av cc v cc v 3 v 2 v 1 com4 com3 com2 com1 seg44 seg43 seg42 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 fp-80b (top view) 21 d 8 44 seg21 22 d 10 / stopc 43 r7 3 /seg20 23 d 11 / int 0 42 r7 2 /seg19 24 r0 0 / int 1 41 r7 1 /seg18
hd404849 series 4 pin description pin number item symbol fp-80a ,tfp-80c fp-80b i/o function power supply v cc 73 75 applies power voltage gnd 10 12 connected to ground test test 4 6 i used for factory testing only: connect this pin to gnd reset reset 7 9 i resets the mcu oscillator osc 1 5 7 i input/output pins for the internal oscillator circuit: connect them to a ceramic oscillator or connect osc1 to an external oscillator circuit. osc 2 68o x1 8 10 i used for a 32.768-khz crystal for clock purposes. if not to be used, fix the x1 pin to vcc and leave the x2 pin open. x2 9 11 o port d 0 ? 8 11?9 13?1 i/o input/output pins addressed by individual bits; pins d 0 ? 8 are high- current pins that can each supply up to 15 ma d 10 , d 11 20, 21 22, 23 i input pins addressable by individual bits r0?3, r6, r7 22?3, 79, 80, 1, 2, 34?1 24?5, 1?, 36?3 i/o input/output pins addressable in 4-bit units interrupt int 0 , int 1 , int 2 , int 3 21?4 23?6 i input pins for external interrupts stop clear stopc 20 22 i input pin for transition from stop mode to active mode serial sck 31 33 i/o serial clock input/output pin si 32 34 i serial receive data input pin so 33 35 o serial transmit data output pin timer tob, toc, tod 26?8 28?0 o timer output pins evnb , evnd 29, 30 31, 32 i event count input pins
hd404849 series 5 pin number item symbol fp-80a, tfp-80c fp-80b i/o function lcd v 1 , v 2 , v 3 70?2 72?4 power pins for lcd driver. the lcd power supply division resistors can be connected and disconnected as controlled by software. voltage conditions are: v cc 3 v 1 3 v 2 3 v 3 3 gnd com1 com4 66?9 68?1 o common signal pins for lcd seg13 seg44 34?5 36?7 o segment signal pins for lcd a/d converter av cc 74 76 power pin for a/d converter: connect it to the same potential as v cc , as physically close to the v cc pin as possible av ss 3 5 ground for av cc : connect it to the same potential as gnd, as physically close to the gnd pin as possible an 0 ?n 7 75?0, 1, 2 77?0, 1? i analog input pins for a/d converter
hd404849 series 6 block diagram system control circuit 1,184 4-bit ram w (2) x (4) spx (4) y (4) spy (4) a (4) b (4) sp (10) program counter (14) instruction decoder alu st (1) ca (1) r7 r6 r3 r2 r1 r0 d lcd display circuit a/d converter serial interface timer d timer c timer b timer a external interrupt control cricuit internal data bus internal address bus internal data bus d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 10 d 11 r0 1 r0 2 r0 3 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 r3 0 r3 1 r3 2 r3 3 r6 0 r6 1 r6 2 r6 3 r7 0 : data bus : signal lines r7 1 r7 2 r7 3 reset test stopc osc 1 osc 2 x1 x2 v cc gnd int 0 d 11 / r0 2 / r1 0 / r1 1 / r1 2 / r2 0 / r2 1 / r2 2 / r2 3 / r3 0 / r3 1 / r3 2 / r3 3 / r6 0 / r1 3 / r0 1 / r0 0 / int 2 int 3 tob evnb toc tod evnd sck si so av cc av ss an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 v1 v2 v3 com1 com2 com3 com4 seg13 seg44 int 1 r0 0 / int 1 /int 2 / stopc / int 0 /tob /toc /tod / evnb /evnd / sck /si /so /an 4 /an 5 /an 6 /an 7 /seg13 /seg14 /seg15 /seg16 /seg17 /seg18 /seg19 /seg20 /int 3 to high- current pins 512 4-bit, 8,192 10-bit, 12,288 10-bit, 16,384 10-bit rom
hd404849 series 7 memory map rom memory map the rom memory map is shown in figure 1 and described below. vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after mcu reset or an interrupt, program execution continues from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000?1fff: HD404848; $0000?2fff: hd4048412; $0000?3fff: hd404849, hd4074849): used for program coding. 0 15 63 4095 8191 12287 16383 $0000 $000f $003f $0fff $1fff $2fff $3fff hd404849/ hd4074849 program area (16,384 words) hd4048412 program area (12,288 words) HD404848 program area (8,192 words) pattern area (4,096 words) zero-page subroutine area (64 words) vector address area (16 words) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 jmpl instruction (jump to reset , stopc routine) jmpl instruction (jump to int routine) jmpl instruction (jump to int routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b, int routine) jmpl instruction (jump to timer c, int routine) 3 jmpl instruction (jump to timer d routine) jmpl instruction (jump to a/d, serial routine) 2 0 1 figure 1 rom memory map
hd404849 series 8 ram memory map the mcu contains a ram area consisting of a memory register area, an lcd data area, a data area, and a stack area. in addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same ram memory space as a ram-mapped register area outside the above areas. the ram memory map is shown in figure 2 and described below. ram-mapped register area ($000?03f): interrupt control bits area ($000?003) this area is used for interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. special function register area ($004?01f, $024?03f) this area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, lcd, and a/d converter, and is used as data control registers for i/o ports. the structure is shown in figures 2 and 5. these registers can be classified into three types: write-only (w), read-only (r), and read/write (r/w). the sem, semd, rem, and remd instructions can be used for the lcd control register (lcr: $01b), but ram bit manipulation instructions cannot be used for other registers. register flag area ($020?023) this area is used for the dton, wdon, and other register flags and interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. memory register (mr) area ($040?04f): consisting of 16 addresses, this area (mr0?r15) can be accessed by register-register instructions (lamr and xmra). the structure is shown in figure 6. lcd data area ($05c?07b): used for storing 32-digit lcd data which is automatically output to lcd segments as display data. data 1 lights the corresponding lcd segment; data 0 extinguishes it. refer to the lcd description for details. data area ($090?21f: HD404848; $090?2ef: hd4048412, hd404849, hd4074849): 464 digits from $090 to $25f have two banks, which can be selected by setting the bank register (v: $03f). before accessing this area, set the bank register to the required value (figure 7). the area from $260 to $2ef is accessed without setting the bank register. stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine call (cal or call instruction) and for interrupts. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. the data to be saved and the save conditions are shown in figure 6. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area is used for data storage.
hd404849 series 9 interrupt control bits area 63 55 54 51 50 49 48 46 45 44 41 40 39 38 37 36 35 32 31 28 27 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 v register port r7 dcr port r6 dcr port r3 dcr port r2 dcr port r1 dcr port r0 dcr port d8 dcr port d4 to d7 dcr port d0 to d3 dcr system clock select register serial mode register b edge sense select register 2 edge sense select register 1 port mode register c port mode register b lcd output register 3 lcd mode register lcd control register a/d data register upper a/d data register lower a/d mode register timer mode register d2 timer mode register c2 timer mode register b2 timer-d timer mode register d1 timer-c timer mode register c1 miscellaneous register timer-b timer mode register b1 timer mode register a serial data register upper serial data register lower serial mode register a port mode register a $03f $037 $036 $033 $032 $031 $030 $02e $02d $02c $029 $028 $027 $026 $025 $024 $023 $020 $01f $01c $01b $018 $017 $016 $015 $014 $013 $012 $011 $010 $00f $00e $00d $00c $00b $00a $009 $008 $007 $006 $005 $004 $003 $000 register flag area (v) (dcr7) (dcr6) (dcr3) (dcr2) (dcr1) (dcr0) (dcd2) (dcd1) (dcd0) (ssr) (smrb) (esr2) (esr1) (pmrc) (pmrb) (lor3) (lmr) (lcr) (adru) (adrl) (amr) (tmd2) (tmc2) (tmb2) (trdu/twdu) (trdl/twdl) (tmd1) (trcu/twcu) (trcl/twcl) (tmc1) (mis) (trbu/twbu) (trbl/twbl) (tmb1) (tma) (sru) (srl) (smra) (pmra) w w w w w w w w w w w w w w w w w w w r r w r/w r/w r/w r/w r/w w r/w r/w w w r/w r/w w w r/w r/w w w timer read register b lower timer read register b upper timer write register b lower timer write register b upper $00a $00b 10 11 timer read register c lower timer read register c upper timer write register c lower timer write register c upper $00e $00f 14 15 timer read register d lower timer read register d upper timer write register d lower timer write register d upper (trbl) (trbu) r r (twbl) (twbu) w w (trcl) (trcu) r r (twcl) (twcu) w w (trdl) (trdu) r r (twdl) (twdu) w w $011 $012 17 18 0 ram mapped register $000 memory register (16 digits) lcd display area (32 digits) data (144 digits) stack (64 digits) data (464 digits 2) v = 0 (bank 0) v = 1 (bank 1) 64 80 $050 92 $05c 124 $07c 144 $090 608 $260 752 $2f0 960 $3c0 1023 $3ff data (464 digits) v = 0 (bank = 0) data (464 digits) v = 1 (bank = 1) $090 $25f the data area has two banks: bank 0 (v = 0) and bank 1 (v = 1) 1. $040 not used not used not used not used not used not used not used not used not used * 2 read only write only read/write r: w: r/w: notes: hd4048412, hd404849, hd4074849 ram mapped register $000 memory register (16 digits) lcd display area (32 digits) stack (64 digits) data (400 digits) $050 $05c $07c $090 $220 $3c0 $3ff $040 not used not used HD404848 not used 0 64 80 92 124 144 544 960 1023 * 1 two registers are mapped to the same address (at $00a, $00b, $00e, $00f, $011, and $012) 2. figure 2 ram memory map
hd404849 series 10 0 1 2 3 bit 3 bit 2 bit 1 bit 0 imta (im of timer a) ifta (if of timer a) im1 (im of int 1 ) if1 (if of int 1 ) imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) imad (im of a/d) ifad (if of a/d) imtd (im of timer d) iftd (if of timer d) $000 $001 $002 $003 (a) interrupt control bits area im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) 32 33 34 35 icsf (input capture status flag) im3 (im of int 3 ) if3 (if of int 3 ) im2 (im of int 2 ) if2 (if of int 2 ) ims (im of serial interface) ifs (if of serial interface) $020 $021 $022 $023 (b) register flag area dton (direct transfer on flag) adsf (a/d start flag) wdon (watchdog on flag) lson (low speed on flag) icef (input capture error flag) rame (ram enable flag) if: im: ie: sp: interrupt request flag interrupt mask interrupt enable flag stack pointer bit 3 bit 2 bit 1 bit 0 iaof (a/d current off flag) not used not used figure 3 configuration of interrupt control bits and register flag areas
hd404849 series 11 ie im lson iaof if icsf icef rame rsp wdon adsf not used dton sem/semd rem/remd tm/tmd allowed allowed allowed not executed allowed allowed not executed allowed inhibited allowed not executed inhibited allowed inhibited allowed not executed in active mode allowed allowed used in subactive mode not executed not executed inhibited note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. the rem or remd instuction must not be executed for adsf during a/d conversion. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st cannot be guaranteed. bits in the interrupt control bits area and register flag area can be set and reset by the sem/semd and rem/remd instructions, and tested with the tm/tmd instructions. other instructions have no effect on these bits. note the following restrictions for each bit. figure 4 usage limitations of ram bit manipulation instructions
hd404849 series 12 bit3 bit2 bit1 bit0 interrupt control bits area $000 $003 smra $005 srl $006 sru $007 tmb1 $009 trbl/twbl $00a trbu/twbu $00b mis $00c tmc1 $00d trcl/twcl $00e trcu/twcu $00f tmd1 $010 trdl/twdl $011 trdu/twdu $012 tmb2 $013 tmc2 $014 tmd2 $015 amr $016 adrl $017 adru $018 lcr $01b lmr $01c lor3 $01f $020 pmrb $024 pmrc $025 esr1 $026 esr2 $027 smrb $028 ssr $029 dcd0 $02c dcd1 $02d dcd2 $02e dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 dcr6 $036 dcr7 $037 v $03f pmra $004 tma $008 $023 r2 2 /si r2 3 /so r2 1 / sck serial transmit clock speed selection 1 timer a/time base clock source selection (timer a) auto reload on/off clock source selection (timer b) timer b register (upper digit) pull-up mos control pmos so control timer c output mode selection analog channel selection a/d conversion period * 1 * 2 lcd power switch lcd display on/off r7/seg17?0 r6/seg13?6 r0 2 /int 3 r0 1 /int 2 d 10 / stopc r2 0 /evnd r1 3 / evnb int 2 detection edge selection * 3 * 4 32-khz oscillation stop * 5 * 6 port d 3 dcr port d 2 dcr port d 1 dcr port d 0 dcr port d 7 dcr port d 6 dcr port d 5 dcr port d 4 dcr port d 8 dcr port r0 3 dcr port r0 2 dcr port r0 1 dcr port r0 0 dcr port r1 3 dcr port r1 2 dcr port r1 1 dcr port r1 0 dcr port r2 3 dcr port r2 2 dcr port r2 1 dcr port r2 0 dcr port r3 3 dcr port r3 2 dcr port r3 1 dcr port r3 0 dcr port r6 3 dcr port r6 2 dcr port r6 1 dcr port r6 0 dcr port r7 3 dcr port r7 2 dcr port r7 1 dcr port r7 0 dcr bank selection auto reload on/off input capture selection serial data register (lower digit) serial data register (upper digit) timer b register (lower digit) interrupt frame period selection clock source selection (timer c) timer c register (lower digit) timer c register (upper digit) clock source selection (timer d) timer d register (lower digit) timer d register (upper digit) timer b output mode selection timer d output mode selection a/d data register (lower digit) a/d data register (upper digit) lcd input clock source selection lcd duty cycle selection register flag area int 3 detection edge selection evnd detection edge selection d 11 / int 0 r0 0 / int 1 4. 5. 6. transmit clock source selection 32-khz oscillation division ratio system oscillation frequency selection 1. 2. 3. lcd display division resistor switch display on/off in watch mode so output level control in idle states notes: auto reload on/off not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used figure 5 special function register area
hd404849 series 13 memory registers 64 65 66 67 68 69 70 71 73 74 75 76 77 78 79 72 $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f 960 $3c0 1023 $3ff mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 $3fc $3fd $3fe $3ff 1020 1021 1022 1023 pc ?c : st: status flag ca: carry flag program counter 13 stack area 0 figure 6 configuration of memory registers and stack area, and stack position bit initial value read/write bit name 3 not used 2 not used 0 0 r/w v0 1 not used v0 0 1 bank area selection bank 0 is selected bank 1 is selected note: after reset, the value in the bank register is 0, and therefore bank 0 is selected. bank register (v: $03f) figure 7 bank register (v)
hd404849 series 14 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 8 and described below. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 8 registers and flags accumulator (a), b register (b): four-bit registers used to hold the results from the arithmetic logic unit (alu) and transfer data between memory, i/o, and other registers. w register (w), x register (x), y register (y): two-bit (w) and four-bit (x and y) registers used for indirect ram addressing. the y register is also used for d-port addressing.
hd404849 series 15 spx register (spx), spy register (spy): four-bit registers used to supplement the x and y registers. carry flag (ca): one-bit flag that stores any alu overflow generated by an arithmetic operation. ca is affected by the sec, rec, rotl, and rotr instructions. a carry is pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. status flag (st): one-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the alu, or result of a bit test. st is used as a branch condition of the br, brl, cal, and call instructions. the contents of st remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the br, brl, cal, or call instruction is read, regardless of whether the instruction is executed or skipped. the contents of st are pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. program counter (pc): 14-bit binary counter that points to the rom address of the instruction being executed. stack pointer (sp): ten-bit pointer that contains the address of the stack area to be used next. the sp is initialized to $3ff by mcu reset. it is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. the top four bits of the sp are fixed at 1111, so a stack can be used up to 16 levels. the sp can be initialized to $3ff in another way: by resetting the rsp bit with the rem or remd instruction. reset the mcu is reset by inputting a low-level voltage to the reset pin. at power-on or when stop mode is cancelled, reset must be low for at least one t rc to enable the oscillator to stabilize. during operation, reset must be low for at least two instruction cycles. initial values after mcu reset are listed in table 1.
hd404849 series 16 table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt flags/mask interrupt enable flag (ie) 0 inhibits all interrupts interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcd0, dcd1) all bits 0 turns output buffer off (to high impedance) (dcd2) - - - 0 (dcr0 dcr3, dcr6, dcr7) all bits 0 port mode register a (pmra) - - 00 refer to description of port mode register a port mode register b (pmrb) - 000 refer to description of port mode register b port mode register c bits 3, 1, 0 (pmrc3, pmrc1, pmrc0) 000 refer to description of port mode register c detection edge select register 1 (esr1) 0000 disables edge detection detection edge select register 2 (esr2) 00 - - disables edge detection timer/ counters, serial interface timer mode register a (tma) 0000 refer to description of timer mode register a timer mode register b1 (tmb1) 0000 refer to description of timer mode register b1 timer mode register b2 (tmb2) - - 00 refer to description of timer mode register b2 timer mode register c1 (tmc1) 0000 refer to description of timer mode register c1 timer mode register c2 (tmc2) - 000 refer to description of timer mode register c2 timer mode register d1 (tmd1) 0000 refer to description of timer mode register d1 timer mode register d2 (tmd2) 0000 refer to description of timer mode register d2
hd404849 series 17 item abbr. initial value contents timer/ serial mode register a (smra) 0000 refer to description of serial mode register a counters, serial mode register b (smrb) - - x0 refer to description of serial mode register b serial prescaler s (pss) $000 interface prescaler w (psw) $00 timer counter a (tca) $00 timer counter b (tcb) $00 timer counter c (tcc) $00 timer counter d (tcd) $00 timer write register b (twbu, twbl) $x0 timer write register c (twcu, twcl) $x0 timer write register d (twdu, twdl) $x0 octal counter 000 a/d a/d mode register (amr) 0000 refer to description of a/d mode register a/d data register (adru, adrl) $80 refer to description of a/d mode register lcd lcd control register (lcr) 0000 refer to description of lcd control register lcd mode register (lmr) 0000 refer to description of lcd duty-cycle/clock control register lcd output register 3 (lor3) - 00 - sets r-port/lcd segment pins to r port mode bit registers low speed on flag (lson) 0 refer to description of operati ng mod es watchdog timer on flag (wdon) 0 refer to description of timer c a/d start flag (adsf) 0 refer to description of a/d converter a/d current off flag (iaof) 0 direct transfer on flag (dton) 0 refer to description of operati ng mod es input capture status flag (icsf) 0 refer to description of timer d input capture error flag (icef) 0 refer to description of timer d others miscellaneous register (mis) 0000 refer to description of operati ng modes, i/o, and serial interface system clock select register bits 2, 1 (ssr2, ssr1) 00 - refer to description of operati ng modes and oscillation circuits bank register (v) - - - 0 refer to description of ram memory map notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. ?indicates that the bit does not exist.
hd404849 series 18 item abbr. status after cancellation of stop modeby stopc input status after cancellation of stop mode by mcu reset status after all other types of reset carry flag (ca) pre-stop-mode values are not guaranteed; values must be initialized by program pre-mcu-reset values are not guaranteed; values must be initialized by program accumulator (a) b register (b) w register (w) y/spx register (y/spx) y/spy register (y/spy) serial data register (srl, sru) a/d data register (adru, l) ram pre-stop-mode values are retained ram enable flag (rame) 1 0 0 port mode register c bit 2 (pmrc2) pre-stop-mode values are retained 00 system clock select register bit 3 (ssr3)
hd404849 series 19 interrupts the mcu has ten interrupt sources: four external signals ( int 0 , int 1 , int 2 , int 3 ), four timer/counters (timers a, b, c, and d), serial interface, and a/d converter. an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. some vector addresses are shared by two different interrupts. they are timer b and int 2 , timer c and int 3 , and a/d converter and serial interface interrupts. so the type of request that has occurred must be checked at the beginning of interrupt processing. interrupt control bits and interrupt processing: locations $000 to $003 and $022 to $023 in ram are reserved for the interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1. a block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the ten interrupt sources are listed in table 3. an interrupt request occurs when the if is set to 1 and the im is set to 0. if the ie is 1 at that point, the interrupt is processed. a priority programmable logic array (pla) generates the vector address assigned to that interrupt source. the interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program. table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset , stopc * $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 timer b, int 2 4 $0008 timer c, int 3 5 $000a timer d 6 $000c a/d, serial 7 $000e note: * the stopc interrupt request is valid only in stop mode.
hd404849 series 20 ie if0 im0 if1 im1 ifta imta iftb imtb iftc imtc iftd imtd $ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,0 $ 002,1 $ 002,2 $ 002,3 $ 003,0 $ 003,1 sequence control ?push pc/ca/st ?reset ie ?jump to vector address priority control logic vector address note: $m,n is ram address $m, bit number n. ifad imad $ 003,2 $ 003,3 int 0 interrupt int 1 interrupt timer a interrupt timer b interrupt timer c interrupt timer d interrupt a/d interrupt if2 im2 if3 im3 $ 022,0 $ 022,1 $ 022,2 $ 022,3 ifs ims $ 023,2 $ 023,3 int 2 interrupt int 3 interrupt serial interrupt interrupt enable flag figure 9 interrupt control circuit
hd404849 series 21 table 3 interrupt processing and activation conditions interrupt source interrupt control bit int 0 int 1 timer a timer b or int 2 timer c or int 3 timer d a/d or serial ie 1111111 if0 im0 1000000 if1 im1 * 100000 ifta imta ** 10000 iftb imtb + if2 im2 *** 1000 iftc imtc + if3 im3 **** 10 0 iftd imtd ***** 10 ifad imad + ifs ims ****** 1 note: bits marked * can be either 0 or 1. their values have no effect on operation. instruction cycles 123456 instruction execution ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: * * stacking the stack is accessed and the ie reset after the instruction is executed, even if it is a two-cycle instruction. figure 10 interrupt processing sequence
hd404849 series 22 power on reset = 0? reset mcu interrupt request? execute instruction pc (pc) + 1 ? pc $0002 ? pc $0004 ? pc $0006 ? pc $0008 ? pc $000a ? pc $000e ? ie = 1? accept interrupt ie 0 stack (pc) stack (ca) stack (st) ? int 0 interrupt? int 1 interrupt? timer a interrupt? timer b/int 2 interrupt? no yes no yes no yes yes yes yes yes yes no no no no ? ? ? (a/d, serial interrupt) pc $000c ? timer d interrupt? yes no no timer c/int 3 interrupt? figure 11 interrupt processing flowchart
hd404849 series 23 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction, as listed in table 4. table 4 interrupt enable flag (ie: $000, bit 0) ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 , int 2 , int 3 ): there are four external interrupt signals. external interrupt request flags (if0?f3: $000, $001, $022): if0 and if1 are set when the signals input to int 0 and int 1 are falling, and if2 and if3 are set when the signals input to int 2 and int 3 are rising or falling, as listed in table 5. the int 2 and int 3 interrupt edges are selected by the detection edge select registers (esr1, esr2: $026, $027) as shown in figures 12 and 13. table 5 external interrupt request flags (if0?f3: $000, $001, $022) if0?f3 interrupt request 0no 1 yes bit initial value read/write bit name 3 0 w esr13 2 0 w esr12 0 0 w esr10 1 0 w esr11 detection edge selection register 1 (esr1: $026) esr11 0 1 esr10 0 1 0 1 int 2 detection edge no detection falling-edge detection rising-edge detection double-edge detection esr13 0 1 esr12 0 1 0 1 int 3 detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. ** * figure 12 detection edge selection register 1 (esr1)
hd404849 series 24 bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 not used 1 not used detection edge selection register 2 (esr2: $027) esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. * * figure 13 detection edge selection register 2 (esr2) external interrupt masks (im0?m3: $000, $001, $022): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. table 6 external interrupt masks (im0?m3: $000, $001, $022) im0?m3 interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $001, bit 2): set by overflow output from timer a, as listed in table 7. table 7 timer a interrupt request flag (ifta: $001, bit 2) ifta interrupt request 0no 1 yes timer a interrupt mask (imta: $001, bit 3): prevents (masks) an interrupt request caused by the timer a interrupt request flag, as listed in table 8.
hd404849 series 25 table 8 timer a interrupt mask (imta: $001, bit 3) imta interrupt request 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 0): set by overflow output from timer b, as listed in table 9. table 9 timer b interrupt request flag (iftb: $002, bit 0) iftb interrupt request 0no 1 yes timer b interrupt mask (imtb: $002, bit 1): prevents (masks) an interrupt request caused by the timer b interrupt request flag, as listed in table 10. table 10 timer b interrupt mask (imtb: $002, bit 1) imtb interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): set by overflow output from timer c, as listed in table 11. table 11 timer c interrupt request flag (iftc: $002, bit 2) iftc interrupt request 0no 1 yes timer c interrupt mask (imtc: $002, bit 3): prevents (masks) an interrupt request caused by the timer c interrupt request flag, as listed in table 12. table 12 timer c interrupt mask (imtc: $002, bit 3) imtc interrupt request 0 enabled 1 disabled (masked)
hd404849 series 26 timer d interrupt request flag (iftd: $003, bit 0): set by overflow output from timer d, or by the rising or falling edge of signals input to evnd when the input capture function is used, as listed in table 13. table 13 timer d interrupt request flag (iftd: $003, bit 0) iftd interrupt request 0no 1 yes timer d interrupt mask (imtd: $003, bit 1): prevents (masks) an interrupt request caused by the timer d interrupt request flag, as listed in table 14. table 14 timer d interrupt mask (imtd: $003, bit 1) imtd interrupt request 0 enabled 1 disabled (masked) serial interrupt request flag (ifs: $023, bit 2): set when data transfer is completed or when data transfer is suspended, as listed in table 15. table 15 serial interrupt request flag (ifs: $023, bit 2) ifs interrupt request 0no 1 yes serial interrupt mask (ims: $023, bit 3): prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. table 16 serial interrupt mask (ims: $023, bit 3) ims interrupt request 0 enabled 1 disabled (masked) a/d interrupt request flag (ifad: $003, bit 2): set at the completion of a/d conversion, as listed in table 17.
hd404849 series 27 table 17 a/d interrupt request flag (ifad: $003, bit 2) ifad interrupt request 0no 1 yes a/d interrupt mask (imad: $003, bit 3): prevents (masks) an interrupt request caused by the a/d interrupt request flag, as listed in table 18. table 18 a/d interrupt mask (imad: $003, bit 3) imad interrupt request 0 enabled 1 disabled (masked)
hd404849 series 28 operating modes the mcu has five operating modes as shown in table 19. the operations in each mode are listed in tables 20 and 21. transitions between operating modes are shown in figure 14. table 19 operating modes and clock status mode name active standby stop watch subactive * 2 activation method reset cancellation, interrupt request stopc cancellation in stop mode, stop/sby instruction in subactive mode (when direct transfer is selected) sby instruction stop instruction when tma3 = 0 stop instruction when tma3 = 1 int 0 or timer a interrupt request from watch mode status system oscillator op op stopped stopped stopped subsystem oscillator op op op * 1 op op cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, stopc input in stop mode reset input int 0 or timer a interrupt request reset input, stop/sby instruction notes: op implies in operation. 1. operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (ssr: $029). 2. subactive mode is an optional function; specify it on the function option list.
hd404849 series 29 table 20 operations in low-power dissipation modes function stop mode watch mode standby mode subactive mode * 2 cpu reset retained retained op ram retained retained retained op timer a reset op op op timer b reset stopped op op timer c reset stopped op op timer d reset stopped op op serial reset stopped * 3 op op a/d reset stopped op stopped lcd reset op * 4 op op i/o reset * 1 retained retained op notes: op implies in operation. 1. output pins are at high impedance. 2. subactive mode is an optional function specified on the function option list. 3. transmission/reception is activated if a clock is input in external clock mode. however, interrupts stop. 4. when a 32-khz clock source is used. table 21 i/o status in low-power dissipation modes output input standby mode, watch mode stop mode active mode, subactive mode d 0 ? 8 retained high impedance input enabled d 10 , d 11 input enabled r0?3, r6, r7 retained or output of peripheral functions high impedance input enabled
hd404849 series 30 reset by reset input or by watchdog timer f osc : f x : cpu : clk : per : oscillate oscillate stop f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate stop f w f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f w f cyc f osc : f x : cpu : clk : per : stop oscillate f sub f w f sub f osc : f x : cpu : clk : per : stop stop stop stop stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop standby mode stop mode (tma3 = 0, ssr3 = 1) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) sby interrupt sby interrupt stop int 0 , timer a * stop 1. interrupt source 2. stop/sby (dton = 1, lson = 0) 3. stop/sby (dton = 0, lson = 0) 4. stop/sby (dton = don? care, lson = 1) f osc : f x : f cyc : f sub : f w : lson: dton: main oscillation frequency suboscillation frequency for time-base f osc /4 f x /8 or f x /4 (software selectable) f x /8 system clock clock for time-base clock for other peripheral functions low speed on flag direct transfer on flag active mode notes: cpu : clk : per : f osc : f x : cpu : clk : per : stop oscillate stop stop stop (tma3 = 0, ssr3 = 0) reset1 reset2 rame = 0 rame = 1 int 0 , timer a (tma3 = 0) stop stopc stopc stop 1 * 2 * 3 * 1 * 4 figure 14 mcu status transitions
hd404849 series 31 active mode: all mcu functions operate according to the clock generated by the system oscillator osc 1 and osc 2 . standby mode: in standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. therefore, the cpu operation stops, but all ram and register contents are retained, and the d or r port status, when set to output, is maintained. peripheral functions such as interrupts, timers, and serial interface continue to operate. the power dissipation in this mode is lower than in active mode because the cpu stops. the mcu enters standby mode when the sby instruction is executed in active mode. standby mode is terminated by a reset input or an interrupt request. if it is terminated by reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and executes the next instruction after the sby instruction. if the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. a flowchart of operation in standby mode is shown in figure 15.
hd404849 series 32 standby oscillator: active peripheral clocks: active all other clocks: stop no yes no yes no yes no yes no yes no yes yes (sby only) watch oscillator: stop suboscillator: active peripheral clocks: stop all other clocks: stop restart processor clocks reset mcu execute next instruction accept interrupt restart processor clocks no yes if = 1, im = 0, and ie = 1? if0 ? im0 = 1? if1 ? im1 = 1? ifta ? imta = 1? iftb ? imtb + if2 ? im2 = 1? iftc ? imtc + if3 ? im3 = 1? iftd ? imtd = 1? no yes ifad ? imad + ifs ? ims = 1? no stop oscillator: stop suboscillator: active/stop peripheral clocks: stop all other clocks: stop reset = 0? stopc = 0? rame = 1 rame = 0 yes yes no no execute next instruction (sby only) (sby only) (sby only) (sby only) reset = 0? figure 15 mcu operation flowchart stop mode: in stop mode, all mcu operations stop and ram data is retained. therefore, the power dissipation in this mode is the least of all modes. the osc 1 and osc 2 oscillator stops. the x1 and x2 oscillator can be selected to operate by setting bit 3 of the system clock select register (ssr: $029; operating: ssr3 = 0, stop: ssr3 = 1) (figure 26). the mcu enters stop mode if the stop instruction is executed in active mode when bit 3 of timer mode register a (tma: $008) is set to 0 (tma3 = 0) (figure 41). stop mode is terminated by a reset input or a stopc input as shown in figure 16. reset or stopc must be applied for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents before entering stop mode are retained,
hd404849 series 33 but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed.

stop mode oscillator internal clock stop instruction execution t res 3 t rc (stabilization period) t res reset or stopc figure 16 timing of stop mode cancellation watch mode: in watch mode, the clock function (timer a) using the x1 and x2 oscillator and the lcd function operate, but other function operations stop. therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. in this mode, the osc 1 and osc 2 oscillator stops, but the x1 and x2 oscillator operates. the mcu enters watch mode if the stop instruction is executed in active mode when tma3 = 1, or if the stop or sby instruction is executed in subactive mode. watch mode is terminated by a reset input or a timer-a/ int 0 interrupt request. for details of reset input, refer to the stop mode section. when terminated by a timer-a/ int 0 interrupt request, the mcu enters active mode if lson = 0, or subactive mode if lson = 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x (where t + t rc < t x < 2t + t rc ) for an int 0 interrupt, as shown in figures 17 and 18. operation during mode transition is the same as that at standby mode cancellation (figure 15).
hd404849 series 34 active mode watch mode active mode oscillation stabilization period interrupt strobe int interrupt request generation (during the transition from watch mode to active mode only) 0 ttt rc tx t: t : rc interrupt frame length oscillation stabilization period figure 17 interrupt frame bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 mis0 t * 0 0.24414 ms t rc 0.12207 ms 0.24414 ms 7.8125 ms 31.25 ms oscillation circuit conditions external clock input ceramic oscillator crystal oscillator 0 1 1 1 0 1 15.625 ms 62.5 ms not used notes: 1. 2. the values of t and t rc are applied when a 32.768-khz crystal oscillator is used. the value is applied only when direct transfer operation is used. buffer control. refer to figure 38. mis3 mis2 1 * 1 * 2 figure 18 miscellaneous register (mis) subactive mode: the osc 1 and osc 2 oscillator stops and the mcu operates with a clock generated by the x1 and x2 oscillator. in this mode, functions except the a/d conversion operate. however, because the operating clock slows down, power dissipation is reduced, next least to watch mode.
hd404849 series 35 the cpu instruction execution speed can be selected as 244 m s or 122 m s by setting bit 2 (ssr2) of the system clock select register (ssr: $029). note that the ssr2 value must be changed in active mode. if the value is changed in subactive mode, the mcu may malfunction. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of the low speed on flag (lson: $020, bit 0) and the direct transfer on flag (dton: $020, bit 3). interrupt frame: in watch and subactive modes, f clk is applied to timer a and the int 0 circuit. prescaler w and timer a operate as the time-base and generate the timing clock for the interrupt frame. three interrupt frame lengths (t) can be selected by setting the miscellaneous register (mis: $00c) (figure 18). in watch and subactive modes, a timer-a/ int 0 interrupt is generated synchronously with the interrupt frame. an interrupt request is generated synchronously with an interrupt strobe except during transition to active mode. the falling edge of the int 0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. an overflow and interrupt request in timer a is generated synchronously with the interrupt strobe. direct transition from subactive mode to active mode: available by controlling the direct transfer on flag (dton: $020, bit 3) and the low speed on flag (lson: $020, bit 0). the procedures are described below: set lson to 0 and dton to 1 in subactive mode. execute the stop or sby instruction. the mcu automatically enters active mode from subactive mode after waiting for the mcu internal processing time and oscillation stabilization time (figure 19). notes: 1. the dton flag ($020, bit 3) can be set only in subactive mode. it is always reset in active mode. 2. the transition time (t d ) from subactive mode to active mode: t rc < t d < t + t rc subactive mode interrupt strobe direct transfer completion timing mcu internal processing period oscillation stabilization time active mode t t rc t: t : rc stop/sby instruction execution (set lson = 0, dton = 1) interrupt frame length oscillation stabilization period figure 19 direct transition timing
hd404849 series 36 stop mode cancellation by stopc : the mcu enters active mode from stop mode by inputting stopc or reset . in either case, the mcu starts instruction execution from the starting address (address 0) of the program. however, the value of the ram enable flag (rame: $021, bit 3) differs between cancellation by stopc and by reset . when stop mode is cancelled by reset , rame = 0; when cancelled by stopc , rame = 1. reset can cancel all modes, but stopc is valid only in stop mode; stopc input is ignored in other modes. therefore, when the program needs to confirm that stop mode has been cancelled by stopc (for example, when the ram contents before entering stop mode are used after transition to active mode), execute the test instruction on the ram enable flag (rame) at the beginning of the program. mcu operation sequence: the mcu operates in the sequence shown in figures 20 to 22. it is reset by an asynchronous reset input, regardless of its status. the low-power mode operation sequence is shown in figure 22. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 0 ? rame = 0 reset mcu mcu operation cycle no yes figure 20 mcu operating sequence (power on)
hd404849 series 37 mcu operation cycle if = 1? instruction execution sby/stop instruction? pc next location pc vector address low-power mode operation cycle ie 0 stack (pc), (ca), (st) im = 0 and ie = 1? ? ? ? yes no no yes yes no if: im: ie: pc: ca: st: ? interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag figure 21 mcu operating sequence (mcu operation cycle)
hd404849 series 38 low-power mode operation cycle if = 1 and im = 0? hardware nop execution ? pc next iocation mcu operation cycle standby/watch mode if = 1 and im = 0? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes for if and im operation, refer to figure 15. stopc = 0? rame = 1 reset mcu no yes figure 22 mcu operating sequence (low-power mode operation) notes on use: when the mcu is in watch mode or subactive mode, if the high level period before the falling edge of int 0 is shorter than the interrupt frame, int 0 will not be detected. also, if the low level period after the falling edge of int 0 is shorter than the interrupt frame, int 0 will not be detected. edge detection is shown in figure 23. the level of the int 0 signal is sampled by a sampling clock. when this sampled value changes from high to low, a falling edge is detected.
hd404849 series 39 in figure 24, the level of the int 0 signal is sampled by an interrupt frame. in (a) the sampled value is low at point a, and also low at point b. therefore, a falling edge will not be detected. in (b), the sampled value is high at point a, and also high at point b. a falling edge will not be detected in this case either. when the mcu is in watch mode or subactive mode, keep the high level and low level period of int 0 longer than the interrupt frame. high low int sampling 0 low figure 23 edge detection a: low b: low int interrupt frame 0 a: high b: high int interrupt frame 0 a. high level period b. low level period figure 24 sampling example
hd404849 series 40 internal oscillator circuit a block diagram of the clock generation circuit is shown in figure 25. as shown in table 22, a ceramic or crystal oscillator can be connected to osc 1 and osc 2 , and a 32.768-khz oscillator can be connected to x1 and x2. the system oscillator can also be operated by an external clock. bit 1 (ssr1) of the system clock select register (ssr: $029) must be set according to the fre quency of the oscillator connected to osc 1 and osc 2 (figure 26). note: if the system clock select register (ssr: $029) setting does not match the oscillator frequency, subsystems using the 32.768-khz oscillation will malfunction. osc 2 osc 1 x1 x2 system oscillator sub- system oscillator 1/4 division circuit timing generator circuit system clock selection cpu with rom, ram, registers, flags, and i/o peripheral function interrupt time-base interrupt time-base clock selection 1/8 or 1/4 division circuit timing generator circuit timing generator circuit 1/8 division circuit f w f sub t subcyc lson tma3 f cyc t cyc f osc f x t wcyc cpu per clk note: * * 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system clock select register (ssr: $029). figure 25 clock generation circuit
hd404849 series 41 bit initial value read/write bit name 3 0 w ssr3 * 2 0 w ssr2 0 not used 1 0 w ssr1 system clock select register (ssr: $029) ssr1 0 1 ssr2 0 1 ratio selection f sub = f x /8 f sub = f x /4 ssr3 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode 32-khz oscillation division system oscillation frequency selection 0.4 mhz ?1.0 mhz 1.6 mhz ?4.5 mhz note: * ssr3 is cleared only by a reset input. ssr3 will not be cleared by a stopc input during stop mode, and will retain its value. ssr3 will also not be cleared upon entering stop mode. figure 26 system clock select register
hd404849 series 42 gnd x2 x1 reset osc 2 osc 1 test gnd figure 27 typical layout of crystal and ceramic oscillators
hd404849 series 43 table 22 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic oscillator gnd ceramic oscillator: csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% crystal oscillator (osc 1 ,osc 2 ) l s c r s c 0 osc 1 osc 2 osc 2 c 1 2 c osc 1 r f crystal oscillator gnd r f = 1 m w 20% c 1 = c 2 = 10 to 22 pf 20% equivalent circuit of crystal oscillator shown at left. c 0 : 7 pf max r s : 100 w max crystal oscillator (x1, x2) x1 c 1 2 c x2 crystal oscillator gnd l s c r s c 0 x1 x2 crystal: 32.768 khz: mx38t (nippon denpa) c 1 = c 2 = 20 pf 20% r s : 14 k w c 0 : 1.5 pf notes: 1. circuit constants differ by the different types of crystal oscillators and ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. the wiring between the osc 1 and osc 2 pins (x1 and x2 pins) and the other elements should be as short as possible, and must not cross other wiring. refer to figure 27. 3. if not using a 32.768-khz crystal oscillator, fix the x1 pin to v cc and leave the x2 pin open.
hd404849 series 44 input/output the mcu has 33 input/output pins (d 0 ? 8 , r0?3, r6, and r7) and two input pins (d 10 , d 11 ). the features are described below. nine pins (d 0 ? 8 ) are high-current input/output pins. the d 10 , d 11 , r0 0 ?0 2 , r1?3, r6, and r7 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. for these pins, the peripheral function setting is done prior to the d or r port setting. therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. peripheral function output pins are cmos output pins. only the r2 3 /so pin can be set to nmos open- drain output by software. in stop mode, the mcu is reset, and therefore peripheral function selection is cancelled. the data control register (dcd, dcr) is also reset, so input/output pins go to the high-impedance state. each input/output pin has a built-in pull-up mos, which can be individually turned on or off by software. i/o buffer configuration is shown in figure 28, programmable i/o circuits are listed in table 23, and i/o pin circuit types are shown in table 24. table 23 programmable i/o circuits mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 01010 101 cmos buffer pmos ?n on nmos on on pull-up mos on?n note: ?indicates off status.
hd404849 series 45 v cc v cc pmos nmos mis3 dcd, dcr pdr cpu input input control signal pull-up mos figure 28 i/o buffer configuration
hd404849 series 46 table 24 circuit configurations of i/o pins i/o pin type circuit pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data mis3 dcd, dcr pdr input control signal d 0 ? 8 r0 0 ?0 3 r1 0 ?1 3 r2 0 ?2 2 r3 0 ?3 3 r6 0 ?6 3 r7 0 ?7 3 v cc v cc pull-up control signal buffer control signal output data input data mis3 dcr pdr input control signal mis2 r2 3 input pins input data input control signal d 10 , d 11 peripheral function pins input/ output pins v cc v cc pull-up control signal output data input data mis3 sck sck sck output pins v cc v cc pull-up control signal pmos control signal output data mis3 so mis2 so v cc v cc pull-up control signal output data mis3 tob, toc, tod tob, toc, tod
hd404849 series 47 i/o pin type circuit pins peripheral function pins input pins input data int 0 , stopc int 0 , stopc hlt mis3 pdr si, etc. v cc si, int 1 , int 2 , int 3 , evnb , evnd a/d input input control an 0 ?n 3 hlt mis3 pdr a/d input input control v cc an 4 ?n 7 note: the mcu is reset in stop mode, and an peripheral function selections are cancelled. the i/o control register is reset, so the input/output pins enter high-impedance state. d port: consist of nine input/output pins and two input pins addressed by one bit. d 0 ? 8 are high-current i/o pins, and d 10 and d 11 are input-only pins. pins d 0 ? 8 are set by the sed and sedd instructions, and reset by the red and redd instructions. output data is stored in the port data register (pdr) for each pin. all pins of the d port are tested by the td and tdd instructions. the on/off statuses of the output buffers are controlled by d port data control registers (dcd0?cd2: $02c?02e) that are mapped to memory addresses (figure 29). pins d 10 and d 11 are multiplexed with peripheral function pins stopc and i nt 0 , respectively. the peripheral function modes of these pins are selected by bits 2 and 3 (pmrc2, pmrc3) of port mode register c (pmrc: $025) (figure 34). r ports: 24 input/output pins addressed in 4-bit units. data is input to these ports by the lar and lbr instructions, and output from them by the lra and lrb instructions. output data is stored in the port data register (pdr) for each pin. the on/off statuses of the output buffers of the r ports are controlled by r port data control registers (dcr0?cr3, dcr6, dcr7: $030?033, $036, $037) that are mapped to memory addresses (figure 29).
hd404849 series 48 pins r0 0 ?0 2 are multiplexed with peripheral pins i nt 1 ?nt 3 , respectively. the peripheral function modes of these pins are selected by bits 0? (pmrb0?mrb2) of port mode register b (pmrb: $024) (figure 30). pins r1 0 ?1 2 are multiplexed with peripheral pins tob, toc, and tod, respectively. the peripheral function modes of these pins are selected by bits 0 and 1 (tmb20, tmb21) of timer mode register b2 (tmb2: $013), bits 0? (tmc20?mc22) of timer mode register c2 (tmc2: $014), and bits 0? (tmd20?md23) of timer mode register d2 (tmd2: $015) (figures 32, 31, and 33). pins r1 3 and r2 0 are multiplexed with peripheral pins evnb and evnd, respectively. the peripheral function modes of these pins are selected by bits 0 and 1 (pmrc0, pmrc1) of port mode register c (pmrc: $025) (figure 34). pins r2 1 ?2 3 are multiplexed with peripheral pins sck , si, and so, respectively. the peripheral function modes of these pins are selected by bit 3 (smra3) of serial mode register a (smra: $005), and bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004), as shown in figures 35 and 36. ports r6 and r7 are multiplexed with segment pins seg13?eg20, respectively. the function modes of these pins can be selected in 4-pin units by setting lcd output register 3 (lor3: $01f) (figure 37).
hd404849 series 49 bit initial value read/write bit name 3 0 w dcd03, 2 0 w dcd02, 0 0 w dcd00, 1 0 w dcd01, dcd0, dcd1 data control register (dcd0 to dcd2: $02c to $02e) (dcr0 to dcr7: $030 to $037) dcd13 dcd12 dcd10 dcd11 bit initial value read/write bit name 3 not used 2 not used 0 0 w dcd20 1 not used dcd2 bit initial value read/write bit name 3 0 w dcr03 2 0 w dcr02 0 0 w dcr00 1 0 w dcr01 dcr0 to dcr3, dcr6, dcr7 dcr33 dcr32 dcr30 dcr31 dcr73 dcr72 dcr70 dcr71 dcr63 dcr62 dcr60 dcr61 correspondence between ports and dcd/dcr bits 0 1 dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr6 dcr7 off (high-impedance) on all bits cmos buffer on/off selection register name d 3 d 7 r0 3 r1 3 r2 3 r3 3 r6 3 r7 3 bit 3 d 2 d 6 r0 2 r1 2 r2 2 r3 2 r6 2 r7 2 bit 2 d 1 d 5 r0 1 r1 1 r2 1 r3 1 r6 1 r7 1 bit 1 d 0 d 4 d 8 r0 0 r1 0 r2 0 r3 0 r6 0 r7 0 bit 0 figure 29 data control registers (dcd, dcr)
hd404849 series 50 bit initial value read/write bit name 3 not used 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 port mode register b (pmrb: $024) pmrb2 0 1 r0 2 /int 3 mode selection r0 2 int 3 pmrb0 0 1 r0 0 / int 1 mode selection r0 0 int 1 pmrb1 0 1 r0 1 /int 2 mode selection r0 1 int 2 figure 30 port mode register b (pmrb) bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 tmc20 0 1 0 1 0 1 0 1 tmc21 0 1 0 1 0 1 r1 1 /toc mode selection r1 1 toc toc toc toc r1 1 port toggle output 0 output 1 output inhibited pwm output figure 31 timer mode register c2 (tmc2)
hd404849 series 51 bit initial value read/write bit name 3 not used 2 not used 0 0 r/w tmb20 1 0 r/w tmb21 timer mode register b2 (tmb2: $013) tmb21 0 1 tmb20 0 1 0 1 r1 0 /tob mode selection r1 0 tob tob tob r1 0 port toggle output 0 output 1 output figure 32 timer mode register b2 (tmb2) bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r1 2 /tod mode selection r1 2 tod tod tod tod r1 2 r1 2 port toggle output 0 output 1 output inhibited pwm output input capture (r1 2 port) tmd23 0 1 don? care don? care don? care figure 33 timer mode register d2 (tmd2)
hd404849 series 52 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 0 w pmrc1 port mode register c (pmrc: $025) pmrc0 0 1 r1 3 r1 3 / evnb mode selection evnb pmrc2 0 1 d 10 stopc pmrc3 0 1 d 11 d 11 / int 0 mode selection int 0 d 10 / stopc mode selection note: pmrc2 is reset to 0 only by reset input. when stopc is input in stop mode, pmrc2 is not reset but retains its value. * * pmrc1 0 1 r2 0 /evnd mode selection r2 0 evnd figure 34 port mode register c (pmrc) bit initial value read/write bit name 3 0 w smra3 2 0 w smra2 0 0 w smra0 1 0 w smra1 serial mode register a (smra: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output output output output output output output input prescaler prescaler prescaler prescaler prescaler prescaler system clock external clock ? 2048 ? 512 ? 128 ? 32 ? 8 ? 2 prescaler division ratio smra2 smra0 smra1 clock source smra3 0 1 r2 1 / sck mode selection sck r2 1 sck figure 35 serial mode register a (smra)
hd404849 series 53 bit initial value read/write bit name 3 not used 2 not used 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r2 3 /so mode selection r2 3 so port mode register a (pmra: $004) pmra1 0 1 r2 2 /si mode selection r2 2 si figure 36 port mode register a (pmra) bit initial value read/write bit name 3 not used 2 0 w lor32 0 not used 1 0 w lor31 lcd output register 3 (lor3: $01f) lor31 0 1 r6/seg13?eg16 mode selection r6 seg13?eg16 lor32 0 1 r7/seg17?eg20 mode selection r7 seg17?eg20 figure 37 lcd output register 3 (lor3) pull-up mos transistor control: a program-controlled pull-up mos transistor is provided for each input/output pin other than input-only pins d 10 and d 11 . the on/off status of all these transistors is controlled by bit 3 (mis3) of the miscellaneous register (mis: $00c), and the on/off status of an individual transistor can also be controlled by the port data register (pdr) of the corresponding pin?nabling on/off control of that pin alone (table 23 and figure 38). the on/off status of each transistor and the peripheral function mode of each pin can be set independently.
hd404849 series 54 bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 cmos buffer on/off selection for pin r2 3 /so miscellaneous register (mis: $00c) 0 1 on off refer to figure 18 in the operation modes section. t rc selection. mis3 0 1 pull-up mos on/off selection off on mis1 mis0 figure 38 miscellaneous register (mis) how to deal with unused i/o pins: i/o pins that are not needed by the user system (floating) must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up mos transistors or by resistors of about 100 k w .
hd404849 series 55 prescalers the mcu has two prescalers, s and w. the prescaler operating conditions are listed in table 25, and the prescalers output supply is shown in figure 39. the timer a? input clocks except external events, the serial transmit clock except the external clock, and the lcd controller/driver operating clock are selected from the prescaler outputs, depending on corresponding mode registers. prescaler operation prescaler s: 11-bit counter that inputs the system clock signal. after being reset to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except in watch and subactive modes and at mcu reset. prescaler w: five-bit counter that inputs the divided x1 input clock signal (32-khz crystal oscillation). after being reset to $00 by mcu reset, prescaler w divides the input clock. prescaler w can be reset by software. table 25 prescaler operating conditions prescaler input clock reset conditions stop conditions prescaler s system clock (in active and standby mode), subsystem clock (in subactive mode) mcu reset mcu reset, stop mode, watch mode prescaler w 32-khz crystal oscillation mcu reset, software mcu reset, stop mode subsystem clock prescaler w lcd timer a timer b timer c timer d system clock prescaler s serial interface clock selector f x /8 f x /4 or f x /8 figure 39 prescaler output supply
hd404849 series 56 timers the mcu has four timer/counters (a to d). timer a: free-running timer timer b: multifunction timer timer c: multifunction timer timer d: multifunction timer timer a is an 8-bit free-running timer. timers b? are 8-bit multifunction timers, whose functions are listed in table 26. the operating modes are selected by software. table 26 timer functions functions timer a timer b timer c timer d clock source prescaler s available available available available prescaler w available external event available available timer functions free-running available available available available time-base available event counter available available reload available available available watchdog available input capture available timer outputs toggle available available available 0 output available available available 1 output available available available pwm available available note: ?implies not available. timer a timer a functions: timer a has the following functions. free-running timer clock time-base the block diagram of timer a is shown in figure 40.
hd404849 series 57 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 tw cyc f tw cyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w figure 40 block diagram of timer a timer a operations: free-running timer operation: the input clock for timer a is selected by timer mode register a (tma: $008). timer a is reset to $00 by mcu reset and incremented at each input clock. if an input clock is applied to timer a after it has reached $ff, an overflow is generated, and timer a is reset to $00. the overflow sets the timer a interrupt request flag (ifta: $001, bit 2). timer a continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. clock time-base operation: timer a is used as a clock time-base by setting bit 3 (tma3) of timer mode register a (tma: $008) to 1. the prescaler w output is applied to timer a, and timer a generates interrupts at the correct timing based on the 32.768-khz crystal oscillation. in this case, prescaler w and timer a can be reset to $00 by software. registers for timer a operation: timer a operating modes are set by the following registers. timer mode register a (tma: $008): four-bit write-only register that selects timer a? operating mode and input clock source as shown in figure 41.
hd404849 series 58 bit initial value read/write bit name 3 0 w tma3 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss pss pss psw psw psw psw psw operating mode timer a mode tma3 tma1 tma2 tma0 source prescaler 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc input clock frequency 0 1 1 32t wcyc 16t wcyc 8t wcyc 2t wcyc 1/2t wcyc time-base mode 0 0 1 1 0 1 1 inhibited psw and tca reset don? care note: 1. 2. 3. 4. t wcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) timer counter overflow output period (seconds) = input clock period (seconds) 256. if psw or tca reset is selected while the lcd is operating, lcd operation halts (power switch goes off and all seg and com pins are grounded). when an lcd is connected for display, the psw and tca reset periods must be set in the program to the minimum. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. figure 41 timer mode register a (tma)
hd404849 series 59 timer b timer b functions: timer b has the following functions. free-running/reload timer external event counter timer output operation (toggle, 0, and 1 outputs) the block diagram of timer b is shown in figure 42. system clock evnb tob timer output control selector prescaler s (pss) clock timer read register bu (trbu) timer read register bl (trbl) timer counter b (tcb) timer write register bu (twbu) timer write register bl (twbl) timer mode register b1 (tmb1) timer mode register b2 (tmb2) timer b interrupt request flag (iftb) per 3 2 internal data bus 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? free-running/ reload control overflow timer output control logic figure 42 block diagram of timer b
hd404849 series 60 timer b operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register b1 (tmb1: $009). timer b is initialized to the value set in timer write register b (twbl: $00a, twbu: $00b) by software and incremented by one at each clock input. if an input clock is applied to timer b after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer b is initialized to its initial value set in timer write register b; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer b interrupt request flag (iftb: $002, bit 0). iftb is reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer b is used as an external event counter by selecting external event input as the input clock source. in this case, pin r1 3 / evnb must be set to evnb by port mode register c (pmrc: $025). timer b is incremented by one at each falling edge of signals input to pin evnb . the other operations are basically the same as the free-running/reload timer operation. timer output operation: the following three output modes can be selected for timer b by setting timer mode register b2 (tmb2: $013). ? toggle ? 0 output ? 1 output by selecting the timer output mode, pin r1 0 /tob is set to tob. the output from tob is reset low by mcu reset. ? toggle output: when toggle output mode is selected, the output level is inverted if a clock is input after timer b has reached $ff. by using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. the output waveform is shown in figure 43 (1). ? 0 output: when 0 output mode is selected, the output level is pulled low if a clock is input after timer b has reached $ff. note that this function must be used only when the output level is high. ? 1 output: when 1 output mode is selected, the output level is set high if a clock is input after timer b has reached $ff. note that this function must be used only when the output level is low.
hd404849 series 61 t (n + 1) t 256 t t (256 ?n) tmc13 = 0 the waveform is always fixed low when n = $ff. t: n: tmc13 = 1 input clock period to counter (the clock source and frequency division ratio are controlled in timer mode registers b1, c1, and d1) the value in timer write registers c and d note: tmd13 = 0 (free-running timer setting) 256 clock cycles 256 clock cycles free-running timer (1) toggle output waveform (timers b, c, and d) (2) pwm output waveform (timers c and d) (256 ?n) clock cycles (256 ?n) clock cycles reload timer tmd13 = 1 (reload timer setting) figure 43 timer output waveform registers for timer b operation: by using the following registers, timer b operation modes are selected and the timer b count is read and written. ? timer mode register b1 (tmb1: $009) ? timer mode register b2 (tmb2: $013) ? timer write register b (twbl: $00a, twbu: $00b) ? timer read register b (trbl: $00a, trbu: $00b) ? port mode register c (pmrc: $025) timer mode register b1 (tmb1: $009): four-bit write-only register that selects the free-running/reload timer function, input clock source, and prescaler division ratio as shown in figure 44. it is reset to $0 by mcu reset.
hd404849 series 62 bit initial value read/write bit name 3 0 w tmb13 2 0 w tmb12 0 0 w tmb10 1 0 w tmb11 timer mode register b1 (tmb1: $009) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmb12 tmb10 tmb11 input clock period and input clock source r1 3 / evnb (external event input) tmb13 0 1 free-running/reload timer selection free-running timer reload timer figure 44 timer mode register b1 (tmb1) writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register b1 write instruction. a timer b initialization by writing to timer write register b (twbl: $00a, twbu: $00b) must be programmed to occur after a mode change becomes valid. timer mode register b2 (tmb2: $013): two-bit read/write register that selects the timer b output mode as shown in figure 45. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 not used 2 not used 0 0 r/w tmb20 1 0 r/w tmb21 timer mode register b2 (tmb2: $013) tmb21 0 1 tmb20 0 1 0 1 r1 0 /tob mode selection r1 0 tob tob tob r1 0 port toggle output 0 output 1 output figure 45 timer mode register b2 (tmb2) timer write register b (twbl: $00a, twbu: $00b): write-only register consisting of a lower digit (twbl) and upper digit (twbu). the lower digit is reset to $0 by mcu reset, but the upper digit value cannot be guaranteed. see figures 46 and 47.
hd404849 series 63 timer b is initialized by writing to timer write register b (twbl: $00a, twbu: $00b). in this case, the lower digit (twbl) must be written to first, but writing only to the lower digit does not change the timer b value. timer b is initialized to the value in timer write register b at the same time the upper digit (twbu) is written to. when timer write register b is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer b. bit initial value read/write bit name 3 0 w twbl3 2 0 w twbl2 0 0 w twbl0 1 0 w twbl1 timer write register b (lower digit) (twbl: $00a) figure 46 timer write register b lower digit (twbl) bit initial value read/write bit name 3 undefined w twbu3 2 undefined w twbu2 0 undefined w twbu0 1 undefined w twbu1 timer write register b (upper digit) (twbu: $00b) figure 47 timer write register b upper digit (twbu) timer read register b (trbl: $00a, trbu: $00b): read-only register consisting of a lower digit (trbl) and upper digit (trbu) that holds the count of the timer b upper digit. see figures 48 and 49. the upper digit (trbu) must be read first. at this time, the count of the timer b upper digit is obtained, and the count of the timer b lower digit is latched to the lower digit (trbl). after this, by reading trbl, the count of timer b when trbu was read can be obtained. bit initial value read/write bit name 3 undefined r trbl3 2 undefined r trbl2 0 undefined r trbl0 1 undefined r trbl1 timer read register b (lower digit) (trbl: $00a) figure 48 timer read register b lower digit (trbl)
hd404849 series 64 bit initial value read/write bit name 3 undefined r trbu3 2 undefined r trbu2 0 undefined r trbu0 1 undefined r trbu1 timer read register b (upper digit) (trbu: $00b) figure 49 timer read register b upper digit (trbu) port mode register c (pmrc: $025): write-only register that selects r1 3 / evnb pin function as shown in figure 50. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 0 w pmrc1 pmrc1 0 1 r2 0 /evnd mode selection r2 0 evnd port mode register c (pmrc: $025) pmrc0 0 1 r1 3 / evnb mode selection r1 3 evnb pmrc3 0 1 d 11 / int 0 mode selection d 11 int 0 pmrc2 0 1 d 10 / stopc mode selection d 10 stopc figure 50 port mode register c (pmrc) timer c timer c functions: timer c has the following functions. free-running/reload timer watchdog timer timer output operation (toggle, 0, 1, and pwm outputs) the block diagram of timer c is shown in figure 51.
hd404849 series 65 watchdog on flag (wdon) system reset signal timer c interrupt request flag (iftc) timer output control logic timer read register cu (trcu) timer output control timer read register cl (trcl) clock timer counter c (tcc) selector system clock prescaler s (pss) overflow internal data bus timer write register cu (twcu) timer write register cl (twcl) timer mode register c1 (tmc1) timer mode register c2 (tmc2) free-running /reload control watchdog timer control logic toc per 2 4 8 32 128 512 1024 2048 3 3 figure 51 block diagram of timer c
hd404849 series 66 timer c operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register c1 (tmc1: $00d). timer c is initialized to the value set in timer write register c (twcl: $00e, twcu: $00f) by software and incremented by one at each clock input. if an input clock is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer c is initialized to its initial value set in timer write register c; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer c interrupt request flag (iftc: $002, bit 2). iftc is reset by software or mcu reset. refer to figure 3 and table 1 for details. watchdog timer operation: timer c is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (wdon: $020, bit 1) to 1. if a program routine runs out of control and an overflow is generated, the mcu is reset. program runaway can be controlled by initializing timer c by software before it reaches $ff. timer output operation: the following four output modes can be selected for timer c by setting timer mode register c2 (tmc2: $014). ? toggle ? 0 output ? 1 output ? pwm output by selecting the timer output mode, pin r1 1 /toc is set to toc. the output from toc is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-b? toggle output. ? 0 output: the operation is basically the same as that of timer-b? 0 output. ? 1 output: the operation is basically the same as that of timer-b? 1 output. ? pwm output: when pwm output mode is selected, timer c provides the variable-duty pulse output function. the output waveform differs depending on the contents of timer mode register c1 (tmc1: $00d) and timer write register c (twcl: $00e, twcu: $00f). the output waveform is shown in figure 43 (2). registers for timer c operation: by using the following registers, timer c operation modes are selected and the timer c count is read and written. ? timer mode register c1 (tmc1: $00d) ? timer mode register c2 (tmc2: $014) ? timer write register c (twcl: $00e, twcu: $00f) ? timer read register c (trcl: $00e, trcu: $00f) timer mode register c1 (tmc1: $00d): four-bit write-only register that selects the free-running/reload timer function, input clock source, and prescaler division ratio as shown in figure 52. it is reset to $0 by mcu reset.
hd404849 series 67 writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register c1 write instruction. a timer c initialization by writing to timer write register c (twcl: $00e, twcu: $00f) must be programmed to occur after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmc13 2 0 w tmc12 0 0 w tmc10 1 0 w tmc11 timer mode register c1 (tmc1: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc12 tmc10 tmc11 tmc13 0 1 free-running/reload timer selection free-running timer reload timer input clock period figure 52 timer mode register c1 (tmc1) timer mode register c2 (tmc2: $014): three-bit read/write register that selects the timer c output mode as shown in figure 53. it is reset to $0 by mcu reset.
hd404849 series 68 bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 0 tmc21 r1 1 /toc mode selection r1 1 toc toc toc toc r1 1 port toggle output 0 output 1 output inhibited pwm output tmc20 0 1 0 1 0 1 0 1 0 1 10 1 figure 53 timer mode register c2 (tmc2) timer write register c (twcl: $00e, twcu: $00f): write-only register consisting of a lower digit (twcl) and upper digit (twcu). see figures 54 and 55. the operation of timer write register c is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). bit initial value read/write bit name 3 0 w twcl3 2 0 w twcl2 0 0 w twcl0 1 0 w twcl1 timer write register c (lower digit) (twcl: $00e) figure 54 timer write register c lower digit (twcl) bit initial value read/write bit name 3 undefined w twcu3 2 undefined w twcu2 0 undefined w twcu0 1 undefined w twcu1 timer write register c (upper digit) (twcu: $00f) figure 55 timer write register c upper digit (twcu)
hd404849 series 69 timer read register c (trcl: $00e, trcu: $00f): read-only register consisting of a lower digit (trcl) and upper digit (trcu) that holds the count of the timer c upper digit. see figures 56 and 57. the operation of timer read register c is basically the same as that of timer read register b (trbl: $00a, trbu: $00b). bit initial value read/write bit name 3 undefined r trcl3 2 undefined r trcl2 0 undefined r trcl0 1 undefined r trcl1 timer read register c (lower digit) (trcl: $00e) figure 56 timer read register c lower digit (trcl) bit initial value read/write bit name 3 undefined r trcu3 2 undefined r trcu2 0 undefined r trcu0 1 undefined r trcu1 timer read register c (upper digit) (trcu: $00f) figure 57 timer read register c upper digit (trcu) timer d timer d functions: timer d has the following functions. free-running/reload timer external event counter timer output operation (toggle, 0, 1, and pwm outputs) input capture timer the block diagram for each operation mode of timer d is shown in figures 58-1 and 58-2.
hd404849 series 70 timer d interrupt request flag (iftd) timer output control logic timer read register du (trdu) timer output control timer read register dl (trdl) clock timer counter d (tcd) selector system clock prescaler s (pss) overflow internal data bus timer write register du (twdu) timer write register dl (twdl) timer mode register d1 (tmd1) timer mode register d2 (tmd2) free-running/ reload control tod edge detection logic edge detection selection register 2 (esr2) edge detection control per 2 3 3 2 4 8 32 128 512 2048 evnd figure 58-1 block diagram of timer d (in reload timer and event counter mode)
hd404849 series 71 selector 2 4 8 32 128 512 2048 3 2 per input capture status flag (icsf) input capture error flag (icef) timer d interrupt request flag (iftd) error control logic edge detection logic timer read register du (trdu) timer read register dl (trdl) read signal clock timer counter d (tcd) overflow system clock edge detection control prescaler s (pss) input capture timer control timer mode register d1 (tmd1) timer mode register d2 (tmd2) edge detection selection register 2 (esr2) evnd internal data bus figure 58-2 block diagram of timer d (in input capture timer mode)
hd404849 series 72 timer d operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register d1 (tmd1: $010). timer d is initialized to the value set in timer write register d (twdl: $011, twdu: $012) by software and incremented by one at each clock input. if an input clock is applied to timer d after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer d is initialized to its initial value set in timer write register d; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer d interrupt request flag (iftd: $003, bit 0). iftd is reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer d is used as an external event counter by selecting the external event input as an input clock source. in this case, pin r2 0 /evnd must be set to evnd by port mode register c (pmrc: $025). either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (esr2: $027). when both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. timer d is incremented by one at each detection edge selected by detection edge select register 2 (esr2: $027). the other operations are basically the same as the free-running/reload timer operation. timer output operation: the following four output modes can be selected for timer d by setting timer mode register d2 (tmd2: $015). ? toggle ? 0 output ? 1 output ? pwm output by selecting the timer output mode, pin r1 2 /tod is set to tod. the output from tod is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-b? toggle output. ? 0 output: the operation is basically the same as that of timer-b? 0 output. ? 1 output: the operation is basically the same as that of timer-b? 1 output. ? pwm output: the operation is basically the same as that of timer-c? pwm output. input capture timer operation: the input capture timer counts the clock cycles between trigger edges input to pin evnd. either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (esr2: $027). when a trigger edge is input to evnd, the count of timer d is written to timer read register d (trdl: $011, trdu: $012), and the timer d interrupt request flag (iftd: $003, bit 0) and the input capture status flag (icsf: $021, bit 0) are set. timer d is reset to $00, and then incremented again. while icsf is set, if a trigger input edge is applied to timer d, or if timer d generates an overflow, the input capture error flag (icef: $021, bit 1) is set. icsf and icef are reset to 0 by mcu reset or by writing 0.
hd404849 series 73 by selecting the input capture operation, pin r1 2 /tod is set to r1 2 and timer d is reset to $00. registers for timer d operation: by using the following registers, timer d operation modes are selected and the timer d count is read and written. ? timer mode register d1 (tmd1: $010) ? timer mode register d2 (tmd2: $015) ? timer write register d (twdl: $011, twdu: $012) ? timer read register d (trdl: $011, trdu: $012) ? port mode register c (pmrc: $025) ? detection edge select register 2 (esr2: $027) timer mode register d1 (tmd1: $010): four-bit write-only register that selects the free-running/reload timer function, input clock source, and prescaler division ratio as shown in figure 59. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register d1 (tmd1: $010) write instruction. a timer d initialization by writing to timer write register d (twdl: $011, twdu: $012) must be programmed to occur after a mode change becomes valid. when selecting the input capture timer operation, select the internal clock as the input clock source.
hd404849 series 74 bit initial value read/write bit name 3 0 w tmd13 2 0 w tmd12 0 0 w tmd10 1 0 w tmd11 timer mode register d1 (tmd1: $010) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmd12 tmd10 tmd11 input clock period and input clock source r2 0 /evnd (external event input) tmd13 0 1 free-running/reload timer selection free-running timer reload timer figure 59 timer mode register d1 (tmd1) timer mode register d2 (tmd2: $015): four-bit read/write register that selects the timer d output mode and input capture operation as shown in figure 60. it is reset to $0 by mcu reset.
hd404849 series 75 bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r1 2 /tod mode selection r1 2 tod tod tod tod r1 2 r1 2 port toggle output 0 output 1 output inhibited pwm output input capture (r1 2 port) tmd23 0 1 don? care don? care don? care figure 60 timer mode register d2 (tmd2) timer write register d (twdl: $011, twdu: $012): write-only register consisting of a lower digit (twdl) and upper digit (twdu). see figures 61 and 62. the operation of timer write register d is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). bit initial value read/write bit name 3 0 w twdl3 2 0 w twdl2 0 0 w twdl0 1 0 w twdl1 timer write register d (lower digit) (twdl: $011) figure 61 timer write register d lower digit (twdl) bit initial value read/write bit name 3 undefined w twdu3 2 undefined w twdu2 0 undefined w twdu0 1 undefined w twdu1 timer write register d (upper digit) (twdu: $012) figure 62 timer write register d upper digit (twdu)
hd404849 series 76 timer read register d (trdl: $011, trdu: $012): read-only register consisting of a lower digit (trdl) and upper digit (trdu). see figures 63 and 64. the operation of timer read register d is basically the same as that of timer read register b (trbl: $00a, trbu: $00b). when the input capture timer operation is selected and if the count of timer d is read after a trigger is input, either the lower or upper digit can be read first. bit initial value read/write bit name 3 undefined r trdl3 2 undefined r trdl2 0 undefined r trdl0 1 undefined r trdl1 timer read register d (lower digit) (trdl: $011) figure 63 timer read register d lower digit (trdl) bit initial value read/write bit name 3 undefined r trdu3 2 undefined r trdu2 0 undefined r trdu0 timer read register d (upper digit) (trdu: $012) 1 undefined r trdu1 figure 64 timer read register d upper digit (trdu) port mode register c (pmrc: $025): write-only register that selects r2 0 /evnd pin function as shown in figure 50. it is reset to $0 by mcu reset. detection edge select register 2 (esr2: $027): write-only register that selects the detection edge of signals input to pin evnd as shown in figure 65. it is reset to $0 by mcu reset.
hd404849 series 77 bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 not used 1 not used detection edge register 2 (esr2: $027) esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. * * figure 65 detection edge select register 2 (esr2) notes on use when using the timer output as pwm output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 27. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle.
hd404849 series 78 table 27 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output free running timer write register updated to value n interrupt request timer write register updated to value n interrupt request t (255 ?n) t (n + 1) t (n' + 1) t (255 ?n) t (n + 1) reload timer write register updated to value n interrupt request timer write register updated to value n interrupt request t t (255 ?n) t t t (255 ?n) t
hd404849 series 79 serial interface the serial interface serially transfers and receives 8-bit data, and includes the following features. multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock output level control in idle states five registers, an octal counter are also configured for the serial interface as follows. ? serial data register (srl: $006, sru: $007) ? serial mode register a (smra: $005) ? serial mode register b (smrb: $028) ? port mode register a (pmra: $004) ? miscellaneous register (mis: $00c) ? octal counter (oc) ? selector the block diagram of the serial interface is shown in figure 66.
hd404849 series 80 internal data bus ? 2 ? 8 ? 32 ? 128 ? 512 ? 2048 serial mode register b (smrb) sck selector system clock per prescaler s (pss) idle controller 3 serial mode register a (smra) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 1/2 si so octal counter (oc) i/o controller transfer control signal figure 66 block diagram of serial interface serial interface operation selecting and changing the operating mode: table 28 lists the serial interface? operating modes. to select an operating mode, use one of these combinations of port mode register a (pmra: $004) and serial mode register a (smra: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register a. note that the serial interface is initialized by writing data to serial mode register a. refer to the following serial mode register a section for details. table 28 serial interface operating modes smra pmra bit 3 bit 1 bit 0 operating mode 1 0 0 clock continuous output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode
hd404849 series 81 pin setting: the r2 1 / sck pin is controlled by writing data to serial mode register a (smra: $005). the r2 2 /si and r2 3 /so pins are controlled by writing data to port mode register a (pmra: $004). refer to the following registers for serial interface section for details. transmit clock source setting: the transmit clock source is set by writing data to serial mode register a (smra: $005) and serial mode register b (smrb: $028). refer to the following registers for serial interface section for details. data setting: serial data is set by writing data to the serial data register (srl: $006, sru, $007). receive data is obtained by reading the contents of the serial data register. the serial data is shifted by the transmit clock and is input from or output to an external system. the output level of the so pin remains unsettled until the first data is output after mcu reset, or until the output level control in idle states is performed. transfer control: the serial interface is activated by the sts instruction. the octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. when the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (ifs: $023, bit 2) is set, and the transfer stops. when the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t cyc to 8192t cyc by setting bits 0 to 2 (smra0?smra2) of serial mode register a (smra: $005) and bit 0 (smrb0) of serial mode register b (smrb: $028) as listed in table 29. table 29 serial transmit clock (prescaler output) smrb smra bit 0 bit 2 bit 1 bit 0 prescaler division ratio transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 100 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 100 ? 16 32t cyc 1 ? 48t cyc
hd404849 series 82 operating states: the serial interface has the following operating states; transitions between them are shown in figure 67. ? sts wait state ? transmit clock wait state ? transfer state ? continuous clock output state (only in internal clock mode) sts wait state: the serial interface enters sts wait state by mcu reset (00, 10 in figure 67). in sts wait state, the serial interface is initialized and the transmit clock is ignored. if the sts instruction is then executed (01, 11), the serial interface enters transmit clock wait state. transmit clock wait state: transmit clock wait state is the period between the sts execution and the falling edge of the first transmit clock. in transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state. however, note that if clock continuous output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters clock continuous output state (17). the serial interface enters sts wait state by writing data to serial mode register a (smra: $005) (04, 14) in transmit clock wait state. transfer state: transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. in transfer state, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters another state. when the sts instruction is executed (05, 15), transmit clock wait state is entered. when eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and sts wait state is entered (13) in internal clock mode. in internal clock mode, the transmit clock stops after outputting eight clocks. in transfer state, writing data to serial mode register a (smra: $005) (06, 16) initializes the serial interface, and sts wait state is entered. if the state changes from transfer to another state, the serial interrupt request flag (ifs: $023, bit 2) is set by the octal counter that is reset to 000. clock continuous output state (only in internal clock mode): clock continuous output state is entered only in internal clock mode. in this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the sck pin. when bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters clock continuous output state. if serial mode register a (smra: $005) is written to in clock continuous output mode (18), sts wait state is entered.
hd404849 series 83 sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) trans fer state (octal counter = 000) mcu reset 00 smra write 04 sts instruction 01 transmit clock 02 8 transmit clocks 03 sts instruction (ifs 1) 05 ? smra write (ifs 1) 06 ? external clock mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) smra write 14 sts instruction 11 transmit clock 12 15 sts instruction (ifs 1) ? 8 transmit clocks 13 internal clock mode clock continuous output state (pmra 0, 1 = 00) smra write 18 transmit clock 17 16 note: refer to the operating states section for the corresponding encircled numbers. mcu reset 10 ? smra write (ifs 1) figure 67 serial interface state transitions output level control in idle states: in idle states, that is, sts wait state and transmit clock wait state, the output level of the so pin can be controlled by setting bit 1 (smrb1) of serial mode register b (smrb: $028) to 0 or 1. the output level control example is shown in figure 68. note that the output level cannot be controlled in transfer state.
hd404849 series 84 state mcu reset pmra write smra write smrb write srl, sru write sts instruction sck pin (input) so pin ifs sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write smra write smrb write srl, sru write sts instruction sck pin (output) so pin ifs sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode figure 68 example of serial interface operation sequence
hd404849 series 85 transmit clock error detection (in external clock mode): the serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. a transmit clock error of this type can be detected as shown in figure 69. if more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (ifs: $023, bit 2) is set, and transmit clock wait state is entered. at the falling edge of the next normal clock signal, the transfer state is entered. after the transfer completion processing is performed and ifs is reset, writing to serial mode register a (smra: $005) changes the state from transfer to sts wait. at this time ifs is set again, and therefore the error can be detected.
hd404849 series 86 transfer completion (ifs1 1) interrupts inhibited ifs1 0 sm1a write ifs1 = 1 transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart transmit clock error detection procedures state transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when smra is written, ifs is set. flag set because octal counter reaches 000 flag reset at transfer completion smra write 12 3 45678 sck pin (input) ifs figure 69 transmit clock error detection
hd404849 series 87 notes on use: initialization after writing to registers: if port mode register a (pmra: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register a (smra: $005) again. setting the serial interrupt request flag (ifs: $023, bit 2): if the state is changed from transfer to another by writing to serial mode register a (smra: $005) or executing the sts instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. to set the serial interrupt request flag, serial mode register a write or sts instruction execution must be programmed to be executed after confirming that the sck pin is at 1, that is, after executing the input instruction to port r2. registers for serial interface the serial interface operation is selected, and serial data is read and written by the following registers. ? serial mode register a (smra: $005) ? serial mode register b (smrb: $028) ? serial data register (srl: $006, sru: $007) ? port mode register a (pmra: $004) ? miscellaneous register (mis: $00c) serial mode register a (smra: $005): this register has the following functions (figure 70). r2 1 / sck pin function selection transfer clock selection prescaler division ratio selection serial interface initialization serial mode register a (smra: $005) is a 4-bit write-only register. it is reset to $0 by mcu reset. a write signal input to serial mode register a (smra: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. therefore, if a write is performed during data transfer, the data transfer is discontinued and the serial interrupt request flag (ifs: $023, bit 2) is set. written data is valid from the second instruction execution cycle after a write operation, so the sts instruction must be executed at least two cycles after a write operation.
hd404849 series 88 bit initial value read/write bit name 3 0 w smra3 2 0 w smra2 0 0 w smra0 1 0 w smra1 serial mode register a (smra: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 smra2 smra0 smra1 smra3 0 1 r2 1 /sck mode selection r2 1 sck output output input clock source prescaler division ratio refer to table 29 sck prescaler system clock external clock figure 70 serial mode register a (smra) serial mode register b (smrb: $028): this register has the following functions (figure 71). prescaler division ratio selection output level control in idle states serial mode register b (smrb: $028) is a 2-bit write-only register. it cannot be written during data transfer. by setting bit 0 (smrb0) of this register, the prescaler division ratio is selected. only bit 0 (smrb0) can be reset to 0 by mcu reset. bit 1 (smrb1) is used to control the output level of the so pin in idle states. the output level changes at the same time that smrb1 is written to.
hd404849 series 89 bit initial value read/write bit name 3 not used 2 not used 0 0 w smrb0 1 undefined w smrb1 smrb0 0 1 transmit clock division ratio prescaler output divided by 2 prescaler output divided by 4 serial mode register b (smrb: $028) smrb1 0 1 output level control in idle states low level high level figure 71 serial mode register b (smrb) serial data register (srl: $006, sru: $007): the serial data register configuration is shown in figures 72 and 73. this register has the following functions. transmission data write and shift receive data shift and read writing data in this register is output from the so pin, lsb first, synchronously with the falling edge of the transmit clock; data is input, lsb first, through the si pin at the rising edge of the transmit clock. input/output timing is shown in figure 74. data cannot be read or written during serial data transfer. if a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. bit initial value read/write bit name 3 undefined r/w sr3 2 undefined r/w sr2 0 undefined r/w sr0 1 undefined r/w sr1 serial data register (lower digit) (srl: $006) figure 72 serial data register (srl)
hd404849 series 90 bit initial value read/write bit name 3 undefined r/w sr7 2 undefined r/w sr6 0 undefined r/w sr4 1 undefined r/w sr5 serial data register (upper digit) (sru: $007) figure 73 serial data register (sru) lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 74 serial interface input/output timing port mode register a (pmra: $004): this register has the following functions (figure 75). r2 2 /si pin function selection r2 3 /so pin function selection port mode register a (pmra: $004) is a 2-bit write-only register, and is reset to $0 by mcu reset. bit initial value read/write bit name 3 not used 2 not used 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r2 3 /so mode selection r2 3 so port mode register a (pmra: $004) pmra1 0 1 r2 2 /si mode selection r2 2 si figure 75 port mode register a (pmra)
hd404849 series 91 miscellaneous register (mis: $00c): this register has the following function (figure 76). r2 3 /so pin pmos control miscellaneous register (mis: $00c) is a 4-bit write-only register and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 1 mis0 0 1 0 1 t rc * 0.12207 ms 0.24414 ms 7.8125 ms 31.25 ms not used mis2 0 1 r2 3 /so pmos on/off selection on off mis3 0 1 pull-up mos on/off selection off on note: * refer to figure 18. figure 76 miscellaneous register (mis)
hd404849 series 92 a/d converter the mcu has a built-in a/d converter that uses successive approximations with a resistor ladder. it can measure eight analog inputs with 8-bit resolution. as shown in the block diagram of figure 77, the a/d converter has a 4-bit a/d mode register, a 4-bit plus 4-bit a/d data register, a 1-bit a/d start flag, and a 1- bit a/d current off flag. comp + an 1 selector 3 reference voltage reference voltage control a/d control logic a/d start flag (adsf) a/d current off flag (iaof) conversion time control hlt (1 in stop, watch, and subactive modes) a/d mode register (amr) a/d data register (adru, adrl) interrupt flag (ifad) encoder internal data bus an 0 an 2 an 3 r3 0 /an 4 r3 1 /an 5 r3 2 /an 6 r3 3 /an 7 av cc av ss d/a figure 77 block diagram of a/d converter
hd404849 series 93 a/d mode register (amr: $016): four-bit write-only register which selects the a/d conversion period and indicates analog input pin information. bit 0 of the a/d mode register selects the a/d conversion period, and bits 1 to 3 select a channel, as shown in figure 78. bit initial value read/write bit name 3 0 w amr3 2 0 w amr2 0 0 w amr0 1 0 w amr1 a/d mode register (amr: $016) amr0 0 1 conversion time 34t cyc 67t cyc amr3 0 0 1 1 0 0 1 1 amr2 0 1 0 1 0 1 0 1 analog input selection an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 amr1 0 0 0 0 1 1 1 1 figure 78 a/d mode register (amr)
hd404849 series 94 a/d data register (adrl: $017, adru: $018): 8-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. this register is not cleared by reset. any data read during a/d conversion is not guaranteed. after the completion of a/d conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 79, 80, and 81). 3210 msb lsb 3210 bit 0 bit 7 adru: $018 adrl: $017 result figure 79 a/d data registers bit initial value read/write bit name 3 0 r adrl3 2 0 r adrl2 0 0 r adrl0 1 0 r adrl1 a/d data register (lower digit) (adrl: $017) figure 80 a/d data register lower digit (adrl) bit initial value read/write bit name a/d data register (upper digit) (adru: $018) 2 0 r adru2 1 0 r adru1 0 0 r adru0 3 1 r adru3 figure 81 a/d data register upper digit (adru)
hd404849 series 95 a/d start flag (adsf: $020, bit 2): one-bit flag that initiates a/d conversion when set to 1. at the completion of a/d conversion, the converted data is stored in the a/d data register and the a/d start flag is cleared. refer to figure 82. bit initial value read/write bit name 3 0 r/w dton 2 0 r/w adsf 0 0 r/w lson 1 0 r/w wdon a/d start flag (adsf: $020, bit 2) 1 0 adsf (a/d start flag) a/d conversion started a/d conversion completed refer to the description of operating modes dton refer to the description of timers wdon refer to the description of operating modes lson figure 82 a/d start flag (adsf) a/d current off flag (iaof: $021, bit 2): by setting this 1-bit flag to 1, the current flowing through the ladder resistor of the a/d converter is cut off during standby and active modes. see figure 83.
hd404849 series 96 bit initial value read/write bit name 3 0 r/w rame 2 0 r/w iaof 0 0 r/w icsf 1 0 r/w icef a/d current off flag (iaof: $021, bit 2) 1 0 refer to description of operating modes rame refer to description of timers icef refer to description of timers icsf iaof (a/d current off flag) current i is cut off. current i flows. ad ad figure 83 a/d current off flag (iaof) note on use: use the sem and semd instructions to write data to the a/d start flag (adsf: $020, bit 2), but make sure that the a/d start flag is not written to during a/d conversion. data read from the a/d data register (adrl: $017, adru: $018) during a/d conversion cannot be guaranteed. the a/d converter does not operate in the stop, watch, and subactive modes because it relies on the clock from osc, which is stopped in these modes. during these low-power dissipation modes, current through the resistor ladder is cut off to decrease the power input. the port data register (pdr) is initialized to 1 by an mcu reset. at this time, if pull-up mos is selected as active by bit 3 of the miscellaneous register (mis3), the port will be pulled up to v cc . when using a shared r port/analog input pin as an input pin, clear pdr to 0. otherwise, if pull-up mos is selected by mis3 and pdr is set to 1, a pin selected by bit 1 of the a/d mode register as an analog pin will remain pulled up.
hd404849 series 97 lcd controller/driver the mcu has an lcd controller and driver which drive 4 common signal pins and 32 segment pins. the controller consists of a ram area in which display data is stored, a display control register (lcr: $01b), and a duty-cycle/clock-control register (lmr: $01c) (figure 84). four duty cycles and the lcd clock are programmable, and a built-in dual-port ram ensures that display data can be automatically transmitted to the segment signal pins without program intervention. if a 32-khz oscillation clock is selected as the lcd clock source, the lcd can even be used in watch mode, in which the system clock stops.
hd404849 series 98 selector internal data bus v cc v1 v2 v3 gnd com1 com2 com3 com4 r6 0 /seg13 r6 1 /seg14 r7 3 /seg20 seg21 seg43 seg44 2 2 32 2 2 lcd segment driver lcd common driver lcd power control circuit lcd power switch lcd output register 3 (lcr3) lcd mode register (lmr) display dual-port ram (32 digits) lcd control register (lcr) pin control display control display data duty cycle selection lcd input clock pin function control circuit figure 84 block diagram of lcd controller/driver
hd404849 series 99 lcd data area and segment data ($05c?07b): as shown in figure 85, each bit of the storage area corresponds to one of four duty cycles. if data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data. bit 3 bit 2 bit 1 bit 0 96 97 98 99 100 101 102 103 104 105 $060 $061 $062 $063 $064 $065 $066 $067 $068 $069 com4 com3 com2 com1 bit 3 bit 2 bit 1 bit 0 92 93 94 95 $05c $05d $05e $05f seg13 seg14 seg15 seg16 seg13 seg14 seg15 seg16 seg13 seg14 seg15 seg16 seg13 seg14 seg15 seg16 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 $06b $06c $06d $06e $06f $070 $071 $072 $073 $074 $075 $076 $077 $078 $079 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 122 123 $07a $07b com4 com3 com2 com1 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg43 seg44 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg17 seg18 seg19 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 $06a 106 figure 85 configuration of lcd ram area (for dual-port ram)
hd404849 series 100 lcd control register (lcr: $01b): four-bit write-only register which controls lcd blanking, on/off switching of the liquid-crystal display? power supply division resistor, display in watch and subactive modes, and connection of the lcd division resistor, as shown in figure 86. blank/display blank: segment signals are turned off, regardless of lcd ram data setting. display: lcd ram data is output as segment signals. power switch on/off off: the power switch is off. on: the power switch is on and v 1 is v cc . watch/subactive mode display off: in watch and subactive modes, all common and segment pins are grounded and the liquid-crystal power switch is turned off. on: in watch and subactive modes, lcd ram data is output as segment signals. lcd power supply division resistor switch off: division resistor is disconnected. on: division resistor is connected. bit initial value read/write bit name 3 0 w lcr3 2 0 w lcr2 0 0 w lcr0 1 0 w lcr1 lcd display control register (lcr: $01b) lcr1 0 1 power switch on/off off on lcr0 0 1 blank/display blank display 0 1 lcd power supply division resistor switch lcr3 on off 0 1 display on/off selection in watch and subactive modes lcr2 off on figure 86 lcd control register (lcr)
hd404849 series 101 lcd duty-cycle/clock control register (lmr: $01c): four-bit write-only register which selects the display duty cycle and lcd clock source, as shown in figure 87. the dependence of frame frequency on duty cycle is listed in table 30. bit initial value read/write bit name 3 0 w lmr3 2 0 w lmr2 0 0 w lmr0 1 0 w lmr1 lcd duty cycle/clock control register (lmr: $01c) lmr3 lmr2 input clock source selection lmr1 0 0 1 1 lmr0 0 1 0 1 duty cycle selection 1/4 duty 1/3 duty 1/2 duty static cl0 (32.768 duty/64: when 32.768-khz oscillation is used) 0 1 1 1 0 1 cl1 (f osc duty cycle/1024) cl2 (f osc duty cycle/8192) cl3 (refer to table 29) 00 figure 87 lcd duty-cycle/clock control register (lmr)
hd404849 series 102 table 30 lcd frame frequencies for different duty cycles frame frequencies duty cycle lmr3 lmr2 f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz static 0 0 cl0 512 hz 512 hz 512 hz 512 hz 1 cl1 390.6 hz 781.3 hz 1953 hz 3906 hz 1 0 cl2 48.8 hz 97.7 hz 244.1 hz 488.3 hz 1 cl3 * 24.4 hz 48.8 hz 122.1 hz 244.1 hz 64 hz 64 hz 64 hz 64 hz 1/2 0 0 cl0 256 hz 256 hz 256 hz 256 hz 1 cl1 195.3 hz 390.6 hz 976.6 hz 1953 hz 1 0 cl2 24.4 hz 48.8 hz 122.1 hz 244.1 hz 1 cl3 * 12.2 hz 24.4 hz 61 hz 122.1 hz 32 hz 32 hz 32 hz 32 hz 1/3 0 0 cl0 170.7 hz 170.7 hz 170.7 hz 170.7 hz 1 cl1 130.2 hz 260.4 hz 651 hz 1302 hz 1 0 cl2 16.3 hz 32.6 hz 81.4 hz 162.8 hz 1 cl3 * 8.1 hz 16.3 hz 40.7 hz 81.4 hz 21.3 hz 21.3 hz 21.3 hz 21.3 hz 1/4 0 0 cl0 128 hz 128 hz 128 hz 128 hz 1 cl1 97.7 hz 195.3 hz 488.3 hz 976.6 hz 1 0 cl2 12.2 hz 24.4 hz 61 hz 122.1 hz 1 cl3 * 6.1 hz 12.2 hz 30.5 hz 61 hz 16 hz 16 hz 16 hz 16 hz note: * the division ratio depends on the value of bit 3 of timer mode register a (tma). upper value: when tma3 = 0, cl3 = f osc duty cycle/16384. lower value: when tma3 = 1, cl3 = 32.768 khz duty cycle/512. lcd output register 3 (lor3: $01f): write-only register used to specify ports r6 and r7 as pins seg13?eg20 in 4-pin units (figure 88).
hd404849 series 103 bit initial value read/write bit name 3 not used 2 0 w lor32 0 not used 1 0 w lor31 lcd output register 3 (lor3: $01f) lor31 0 1 r6/seg13?eg16 mode selection r6 seg13?eg16 lor32 0 1 r7/seg17?eg20 mode selection r7 seg17?eg20 figure 88 lcd output register 3 (lor3) large liquid-crystal panel drive and v lcd : if the capacitance of the lcd is very large while being driven, decrease the capacitance by attaching external resistors in parallel, as shown in figure 89. the size of these resistors cannot be simply calculated from the lcd load capacitance because the matrix configuration of the lcd complicates the paths of charge/discharge currents flowing through the capacitors?he resistance will also vary with lighting conditions. this size must be determined by trial- and-error, taking into account the power dissipation of the device using the lcd, but a resistance of 1 to 10 k w is usually suitable. (another effective method is to attach capacitors of 0.1 to 0.3 m f.) always turn off the power switch (set bit 1 of the lcr to 0) before changing the liquid-crystal drive voltage (v lcd ).
hd404849 series 104 32 2 3 4 32 32 32 v cc v 2 v 3 gnd v 1 com1 seg13 to seg44 v cc v 2 v 3 gnd v 1 com1 com2 seg13 to seg44 v cc v 2 v 3 gnd v 1 com1 to com3 seg13 to seg44 v cc v 2 v 3 gnd v 1 com1 to com4 seg13 to seg44 v cc v lcd v cc v lcd v cc v lcd v cc v lcd r r r v (v ) cc 1 v 2 v 3 gnd r r r v (v ) cc 1 v 2 v 3 gnd c c c 4-digit lcd . 8-digit lcd 10-digit lcd with sign 16-digit lcd . . . static drive 1/2 duty, 1/2 bias drive 1/3 duty, 1/3 bias drive 1/4 duty, 1/3 bias drive v v gnd cc lcd 3 3 1 figure 89 lcd connection examples
hd404849 series 105 programmable rom (hd4074849) the hd4074849 is a ztat microcomputer with built-in prom that can be programmed in prom mode. pin description by mode pin no. mcu mode prom mode pin no mcu mode prom mode fp-80a, tfp- 80c fp-80b pin name i/o pin name i/o fp- 80a, tfp-80c fp-80b pin name i/o pin name i/o 13r3 2 /an 6 i/o a 3 i28 30 r1 2 /tod i/o a 7 i 24r3 3 /an 7 i/o a 4 i29 31 r1 3 / evnb i/o a 8 i 35av ss gnd 30 32 r2 0 /evnd i/o a 0 i 4 6 test i test i 31 33 r2 1 / sck i/o o 0 i/o 5 7 osc 1 iv cc 32 34 r2 2 /si i/o o 1 i/o 6 8 osc 2 o3335r2 3 /so i/o o 2 i/o 79 reset i reset i34 36 r6 0 /seg13 i/o o 3 i/o 8 10 x1 i gnd 35 37 r6 1 /seg14 i/o o 4 i/o 9 11 x2 o 36 38 r6 2 /seg15 i/o o 4 i/o 10 12 gnd gnd 37 39 r6 3 /seg16 i/o o 3 i/o 11 13 d 0 i/o ce i38 40 r7 0 /seg17 i/o o 2 i/o 12 14 d 1 i/o oe i39 41 r7 1 /seg18 i/o o 1 i/o 13 15 d 2 i/o v cc 40 42 r7 2 /seg19 i/o o 0 i/o 14 16 d 3 i/o v cc 41 43 r7 3 /seg20 i/o v cc 15 17 d 4 i/o a 10 i 42 44 seg21 o 16 18 d 5 i/o a 11 i 43 45 seg22 o 17 19 d 6 i/o a 12 i 44 46 seg23 o 18 20 d 7 i/o a 13 i 45 47 seg24 o 19 21 d 8 i/o a 14 i 46 48 seg25 o 20 22 d 10 / stopc ia 9 i 47 49 seg26 o 21 23 d 11 / int 0 iv pp 48 50 seg27 o 22 24 r0 0 / int 1 i/o m 0 i 49 51 seg28 o 23 25 r0 1 /int 2 i/o m 1 i 50 52 seg29 o 24 26 r0 2 /int 3 i/o 51 53 seg30 o 25 27 r0 3 i/o 52 54 seg31 o 26 28 r1 0 /tob i/o a 5 i 53 55 seg32 o 27 29 r1 1 /toc i/o a 6 i 54 56 seg33 o
hd404849 series 106 pin no. mcu mode prom mode pin no mcu mode prom mode fp-80a, tfp- 80c fp-80b pin name i/o pin name i/o fp- 80a, tfp-80c fp-80b pin name i/o pin name i/o 55 57 seg34 o 68 70 com3 o 56 58 seg35 o 69 71 com4 o 57 59 seg36 o 70 72 v1 58 60 seg37 o 71 73 v2 59 61 seg38 o 72 74 v3 60 62 seg39 o 73 75 v cc v cc 61 63 seg40 o 74 76 av cc v cc 62 64 seg41 o 75 77 an0 i 63 65 seg42 o 76 78 an1 i 64 66 seg43 o 77 79 an2 i 65 67 seg44 o 78 80 an3 i 66 68 com1 o 79 1 r3 0 /an 4 i/o a 1 i 67 69 com2 o 80 2 r3 1 /an 5 i/o a 2 i notes: 1. i/o: input/output pin, i: input pin, o: output pin 2. each of o 0 ? 4 has two pins; before using, each pair must be connected together. prom mode pin functions v pp : applies the programming voltage (12.5 v 0.3 v) to the built-in prom. ce : inputs a control signal to enable prom programming and verification. oe : inputs a data output control signal for verification. a 0 ? 14 : act as address input pins of the built-in prom. o 0 ? 4 : act as data bus input pins of the built-in prom. each of o 0 ? 4 has two pins; before using these pins, connect each pair together. m 0 , m 1 , reset , test: used to set prom mode. the mcu is set to prom mode by pulling m 0 , m 1 , and reset low, and test high. other pins: connect pins av cc , osc 1 , d 2 , d 3 , r7 3 /seg20, and v cc to v cc . connect pins av ss and x1 to gnd. leave other pins open. programming the built-in prom the mcu? built-in prom is programmed in prom mode. prom mode is set by pulling reset , m 0 , and m 1 low, and test high. in prom mode, the mcu does not operate, but it can be programmed in the
hd404849 series 107 same way as any other commercial 27256-type eprom using a standard prom programmer and an 80-to- 28-pin socket adapter. recommended prom programmers and socket adapters are listed in table 31. since an hmcs400-series instruction is ten bits long, the hmcs400-series mcu has a built-in conversion circuit to enable the use of a general-purpose prom programmer. as shown in figure 90, this circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. this means that if, for example, 16 kwords of built-in prom are to be programmed by a general-purpose prom programmer, a 32-kbyte address space ($0000?7fff) must be specified. table 31 recommended prom programmers and socket adapters prom programmer manufacturer model name data i/o corp. 121b 29b aval corp. pkw?000 socket adapter package model name manufacturer fp-80a hs4849esh01h hitachi fp-80b hs4849esf01h tfp-80c hs4849esn01h warnings 1. always specify addresses $0000 to $7fff when programming with a prom programmer. if address $8000 or higher is accessed, the prom may not be programmed or verified correctly. set all data in unused addresses to $ff. note that the plastic-package version cannot be erased and reprogrammed. 2. make sure that the prom programmer, socket adapter, and lsi are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the lsi. before starting programming, make sure that the lsi is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. prom programmers have two voltages (v pp ): 12.5 v and 21 v. remember that hitachi devices require a v pp of 12.5 v?he 21-v setting will damage them. 12.5 v is the intel 27256 setting. programming and verification the built-in prom of the mcu can be programmed at high speed without risk of voltage stress or damage to data reliability.
hd404849 series 108 programming and verification modes are selected as listed in table 32, the memory map in prom mode is shown in figure 90. table 32 prom mode selection pin mode ce oe v pp o 0 ? 4 programming low high v pp data input verification high low v pp data output programming inhibited high high v pp high impedance $0000 vector address zero-page subroutine (64 words) pattern (4,096 words) program (16,384 words) $0001 $001f $0080 $007f $2000 $1fff $0020 $7fff bit 4 bit 8 bit 3 bit 7 bit 2 1 bit 6 bit 1 bit 5 1 1 1 1 1 bit 0 bit 9 upper three bits are not to be used (fill them with 111) upper 5 bits lower 5 bits $0000 $000f $0010 $003f $0040 $3fff . . . . . . . . . $0fff $1000 figure 90 memory map in prom mode
hd404849 series 109 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 91 and described below. ap 9 ap 0 w 1 y 0 w register x register y register ram address register indirect addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 91 ram addressing modes register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. when the area from $090 to $25f is used, a bank must be selected by the bank register (v: $03f). direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address.
hd404849 series 110 memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 92 and described below. d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc pc 10 11 12 13 program counter direct addressing zero page addressing d 5 d 4 d 3 d 2 d 1 d 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10 11 12 13 program counter 00 00 0 0 0 0 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc 10 11 12 13 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 0 0 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pc pc pc 11 12 13 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 92 rom addressing modes
hd404849 series 111 direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 94. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ra ra ra 10 11 12 13 b 2 b 3 b register 0 0 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data r2 3210 3 21 0 if ro = 1 9 output registers r1, r2 r2 r2 r2 r1 r1 r1 r1 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 93 p instruction
hd404849 series 112 br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 94 branching when the branch destination is on a page boundary note that the hmcs400-series cross macroassembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four- bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 93. if bit 8 of the rom data is 1, the lower eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, the lower eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter.
hd404849 series 113 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v total permissible input current ? i o 100 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 ma 4, 5 30 ma 4, 6 maximum output current ? o 4 ma 7, 8 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to d 11 (v pp ) of the hd4074849. 2. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to ground. 3. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 4. the maximum input current is the maximum current flowing from each i/o pin to ground. 5. applies to r0?3, r6, and r7. 6. applies to d 0 ? 8 . 7. the maximum output current is the maximum current flowing out from v cc to each i/o pin. 8. applies to d 0 ? 8 , r0?, r6, and r7.
hd404849 series 114 electrical characteristics dc characteristics (HD404848/hd4048412/hd404849: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074849: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih reset , sck , si, int 0 , int 1 , int 2 , int 3 , stopc , evnb , evnd 0.9v cc ? cc + 0.3 v osc 1 v cc ?0.3 v cc + 0.3 v external clock operation input low voltage v il reset , sck , si, int 0 , int 1 , int 2 , int 3 , stopc , evnb , evnd ?.3 0.1v cc v osc 1 ?.3 0.3 v external clock operation output high voltage v oh sck , so, tob, toc, tod v cc ?1.0 v i oh = 0.5 ma output low voltage v ol sck , so, tob, toc, tod 0.4 v i ol = 0.4 ma i/o leakage current |i il | reset , sck , si, int 0 , int 1 , int 2 , int 3 , stopc , evnb , evnd, osc 1 , tob, toc, tod, so 1.0 m av in = 0 v to v cc 1 current dissipation in active mode i cc1 v cc ?6mav cc = 5.0 v, f osc = 4 mhz 2 i cc2 v cc 0.6 1.8 ma v cc = 3.0 v, f osc = 800 khz 2 current dissipation in standby mode i sby1 v cc 1.0 2.0 ma v cc = 5.0 v, f osc = 4 mhz, lcd on 3 i sby2 v cc 0.2 0.7 ma v cc = 3.0 v, f osc = 800 khz lcd on 3
hd404849 series 115 item symbol pin(s) min typ max unit test condition notes current dissipation in subactive mode i sub v cc ?550 m av cc = 3.0 v, lcd on 4, 7, 8 ?570 m av cc = 3.0 v, lcd on 5, 7, 8 70 150 m av cc = 3.0 v, lcd on 6, 7, 8 current dissipation in watch mode i wtc1 v cc ?540 m av cc = 3.0 v, lcd on 8 i wtc2 v cc ?10 m av cc = 3.0 v, lcd off 8 current dissipation in stop mode i stop v cc 5 m av cc = 3.0 v no 32-khz oscillator 8 stop mode retaining voltage v stop v cc 1.5 v no 32-khz oscillator 9 notes: 1. output buffer current is excluded. 2. i cc1 and i cc2 are the source currents when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset and test at gnd 3. i sby1 and i sby2 are the source currents when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset standby mode pins: reset at v cc test at gnd d 0 ? 8 , d 10 , d 11 , r0?3, r6, r7 at v cc 4. applies to HD404848. 5. applies to hd4048412 and hd404849. 6. applies to hd4074849. 7. when the lcd power supply division resistor is connected (lcr3 = 0). 8. these are the source currents when no i/o current is flowing. test conditions: pins: reset at v cc test at gnd d 0 ? 8 , d 10 , d 11 , r0?3, r6, r7 at v cc 9. test condition voltage necessary for ram data retention.
hd404849 series 116 i/o characteristics for standard pins (HD404848/hd4048412/hd404849: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074849: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih d 10 , d 11 , r0?3, r6, r7 0.7v cc ? cc + 0.3 v input low voltage v il d 10 , d 11 , r0?3, r6, r7 ?.3 0.3v cc v output high voltage v oh r0?3, r6, r7 v cc ?1.0 v i oh = 0.5 ma output low voltage v ol r0?3, r6, r7 0.4 v i ol = 0.4 ma i/o leakage current |i il |d 10 , r0?3, r6, r7 1 m av in = 0 v to v cc 1 d 11 1 m av in = 0 v to v cc 1, 2 1 m av in = v cc ?0.3 v to v cc 1, 3 20 m av in = 0 v to 0.3 v 1, 3 pull-up mos current ? pu r0?3, r6, r7 10 50 150 m av cc = 3.0 v, v in = 0 v notes: 1. output buffer current is excluded. 2. applies to HD404848, hd4048412, and hd404849. 3. applies to hd4074849.
hd404849 series 117 i/o characteristics for high-current pins (HD404848/hd4048412/hd404849: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074849: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition note input high voltage v ih d 0 ? 8 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 8 ?.3 0.3v cc v output high voltage v oh d 0 ? 8 v cc ?1.0 v i oh = 0.5 ma output low voltage v ol d 0 ? 8 0.4 v i ol = 0.4 ma 2.0 v i ol = 15 ma, v cc = 4.5 v to 6.0 v 1 i/o leakage current |i il |d 0 ? 8 1 m av in = 0 v to v cc 2 pull-up mos current ? pu d 0 ? 8 10 50 150 m av cc = 3 v, v in = 0 v note: 1. the test condition of hd4074849 is v cc = 4.5 v to 5.5 v. 2. output buffer current is excluded. lcd circuit characteristics (HD404848/hd4048412/hd404849: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074849: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition note segment driver voltage drop v ds seg13?eg44 0.6 v i d = 3 m a1 common driver voltage drop v dc com1?om4 0.3 v i d = 3 m a1 lcd power supply division resistance r w 50 300 900 k w between v 1 and gnd lcd voltage v lcd v1 2.7 v cc v2 notes: 1. v ds and v dc are the voltage drops from power supply pins v1, v2, v3, and gnd to each segment pin and each common pin, respectively. 2. when v lcd is supplied from an external source, the following relations must be retained: v cc 3 v1 3 v2 3 v3 3 gnd
hd404849 series 118 a/d converter characteristics (HD404848/hd4048412/hd404849: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074849: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition note analog power voltage av cc av cc v cc ?0.3 v cc v cc + 0.3 v 1 analog input voltage av in an 0 ?n 7 av ss ?v cc v current between av cc and av ss i ad 200 m av cc = av cc = 5.0 v analog input capacitance ca in an 0 ?n 7 15 pf resolution 8 8 8 bit number of inputs 0 8 channel absolute accuracy 2.0 lsb conversion time 34 67 t cyc input impedance an 0 ?n 7 1m w note: 1. connect to v cc when the a/d converter is not used.
hd404849 series 119 ac characteristics (HD404848/hd4048412/hd404849: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074849: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition note clock oscillation frequency f osc osc 1 , osc 2 0.4 4.5 mhz 1/4 division 1 x1, x2 32.768 khz instruction cycle time t cyc 0.89 10 m s t subcyc 244.14 m s 32-khz oscillator, 1/8 division 2 122.07 m s 32-khz oscillator, 1/4 division 2 oscillation stabilization time (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 3 oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 30 ms 3 x1, x2 2 s t a = ?0 c to+60 c3 external clock high width t cph osc 1 105 ns f osc = 4 mhz 4 external clock low width t cpl osc 1 105 ns f osc = 4 mhz 4 external clock rise time t cpr osc 1 20 ns f osc = 4 mhz 4 external clock fall time t cpf osc 1 20 ns f osc = 4 mhz 4 int 0 ?nt 3 , evnb , evnd high widths t ih int 0 ?nt 3 , evnb , evnd 2 t cyc / t subcyc ? int 0 ?nt 3 , evnb , evnd low widths t il int 0 ?nt 3 , evnb , evnd 2 t cyc / t subcyc ? reset low width t rstl reset 2 t cyc ? stopc low width t stpl stopc 1 t rc ? reset rise time t rstr reset 20 ms 6 stopc rise time t stpr stopc 20 ms 7 input capacitance c in all pins except d 11 15 pf f = 1 mhz, v in = 0 v d 11 180 pf f = 1 mhz, v in = 0 v 8 notes: 1. when the subsystem oscillator (32.768-khz crystal oscillator) is used, f osc must operate under one of the following conditions: 0.4 mhz f osc 1.0 mhz or 1.6 mhz f osc 4.5 mhz. set bit 1 of the system clock select register (ssr: $029) to 0 for the former, and 1 for the latter. 2. for the HD404848, hd4048412, and hd404849, instructions can be executed during subactive mode if v cc = 2.2 v to 6.0 v. 3. the oscillation stabilization time is defined as the time required for the oscillator to stabilize in the following three cases: after v cc reaches 2.7 v at power-on after reset input goes low when stop mode is cancelled
hd404849 series 120 after stopc input goes low when stop mode is cancelled at power-on or when stop mode is cancelled, reset or stopc must be input for at least t rc to ensure the oscillation stabilization time. if using a ceramic or crystal oscillator, contact its manufacturer to determine what stabilization time is required since it will depend on the circuit constants and stray capacitances. 4. see figure 95. 5. see figure 96. 6. see figure 97. 7. see figure 98. 8. the max value for the HD404848, hd4048412, hd404849 is 15 pf. serial interface timing characteristics (HD404848/hd4048412/hd404849: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074849: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) during transmit clock output item symbol pin min typ max unit test condition note transmit clock cycle time t scyc sck 1.0 t cyc load shown in figure 100 1 transmit clock high width t sckh sck 0.4 t scyc load shown in figure 100 1 transmit clock low width t sckl sck 0.4 t scyc load shown in figure 100 1 transmit clock rise time t sckr sck 100 ns load shown in figure 100 1 transmit clock fall time t sckf sck 100 ns load shown in figure 100 1 serial output data delay time t dso so 300 ns load shown in figure 100 1 serial input data setup time t ssi si 200 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. refer to figure 99.
hd404849 series 121 during transmit clock input item symbol pin min typ max unit test condition note transmit clock cycle time t scyc sck 1.0 t cyc ? transmit clock high width t sckh sck 0.4 t scyc ? transmit clock low width t sckl sck 0.4 t scyc ? transmit clock rise time t sckr sck 100 ns 1 transmit clock fall time t sckf sck 100 ns 1 transmit output data delay time t dso so 300 ns load shown in figure 100 1 serial input data setup time t ssi si 200 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. refer to figure 99. t cpr t cpf v cc ?0.3 v 0.3 v osc 1 t cph t cpl 1/f cp figure 95 external clock timing 0.9v cc 0.1v cc int 0 to int 3 , evnb , evnd t ih t il figure 96 interrupt timing t rstr t rstl 0.9v cc 0.1v cc reset figure 97 reset timing t stpr t stpl 0.9v cc 0.1v cc stopc figure 98 stopc timing
hd404849 series 122 0.9v cc 0.1v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.4 v v ?0.5 v cc v ?2.0 v (0.9v ) cc 0.4 v (0.1v ) sck so si note: v cc ?2.0 v and 0.4 v are the threshold voltages for transmit clock output, and 0.9v cc and 0.1v cc are the threshold voltages for transmit clock input. cc cc t sckh * * * figure 99 serial interface timing r l = 2.6 k w v cc 1s2074 h or equivalent r = 12 k w test point c = 30 pf figure 100 timing load circuit
hd404849 series 123 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size as a 16-kword version (hd404849). a 16-kword data size is required to change rom data to mask manufacturing data since the program used is for a 16-kword version. this limitation applies when using an eprom or a data base. vector address zero-page subroutine (64 words) pattern & program (8,192 words) not used vector address zero-page subroutine (64 words) pattern & program (12,288 words) not used 8-kword rom version: HD404848 write all-1 data to addresses $2000 to $3fff 12-kword rom version: hd4048412 write all-1 data to addresses $3000 to $3fff $0000 $000f $0010 $003f $0040 $1fff $2000 $3fff $0000 $000f $0010 $003f $0040 $2fff $3000 $3fff write all-1 data in shaded areas
hd404849 series 124 HD404848/hd4048412/hd404849 option list HD404848 hd4048412 hd404849 1. rom size 3. rom code media eprom: the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. with 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, without time-base 2. optional functions * * date of order customer department name rom code name lsi number / / 4. oscillator for osc1 and osc2 ceramic oscillator crystal oscillator external clock f = f = f = mhz mhz mhz fp-80a fp-80b tfp-80c 6. package note: used not used 5. stop mode options marked with an asterisk require a subsystem crystal oscillator (x1, x2). please check off the appropriate applications and enter the necessary information. 8-kword 12-kword 16-kword * please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version).
hd404849 series 125 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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